nx_simd_sse_shuf_gate.nx source

1// nx_simd_sse_shuf_gate.nx -- SOVEREIGN 128-bit pshufd run-KAT (rung R2+R3: 2// 3-OPERAND assembler + packed dword shuffle), on REAL x86 silicon, NO gcc/ 3// qemu/binutils. AUTHOR=ORGAN, no-false-green. 4// 5// Proves (a) the assembler now parses a THIRD operand (the prerequisite for 6// pshufd AND all VEX/EVEX 256/512-bit ops), and (b) pshufd routes lanes by its 7// imm control byte. src=[11,22,33,44] (4x u32): 8// POS: pshufd $2 -> dst lane0 = src[2] = 33 -> exit(33). 9// NEG: pshufd $0 -> dst lane0 = src[0] = 11 -> exit(11). 10// GREEN iff pos==33 AND neg==11 AND pos!=neg (distinct => the imm genuinely 11// selects the lane, and op0=imm/op1=src/op2=dst threaded correctly). Completes 12// the sovereign 128-bit integer SIMD surface. license_tier: ORIGINAL 13import "nx_syscalls.nx" 14import "nx_gate_verdict.nx" 15 16const ASM_TOOL: *u8 = "_offc/nxasm_x86_main.elf" 17const SV_LOG: *u8 = "knowledge/status/simd_vec_kat.log" 18 19func gw(fd: i64, s: *u8) -> i64 { var n: i64 = 0; while s[n] != (0 as u8) { n = n + 1 } sys_write(fd, s, n); return 0 } 20func gwn(fd: i64, v: i64) -> i64 { 21 let bb: *u8 = sys_mmap(28); var m: i64 = v 22 if m < 0 { m = 0 - m; sys_write(fd, "-" as *u8, 1) } 23 let t: *u8 = sys_mmap(28); var k: i64 = 0 24 if m == 0 { t[0] = 48; k = 1 } 25 while m > 0 { t[k] = (48 + (m % 10)) as u8; m = m / 10; k = k + 1 } 26 var i: i64 = 0 27 while i < k { bb[i] = t[k - 1 - i]; i = i + 1 } 28 sys_write(fd, bb, k); return 0 29} 30 31func g_run(path: *u8, argv: *i64) -> i64 { 32 let envp: *i64 = sys_mmap(8 * 4) as *i64 33 envp[0] = "PATH=/usr/bin:/bin" as *u8 as i64 34 envp[1] = 0 35 let dn: i64 = sys_openat_wr("/dev/null" as *u8, 0x1a4) 36 let pid: i64 = sys_fork() 37 if pid == 0 { 38 if dn >= 0 { sys_dup3(dn, 1, 0) } 39 if dn >= 0 { sys_dup3(dn, 2, 0) } 40 sys_execve(path, argv, envp) 41 sys_exit(127) 42 } 43 let st: *i64 = sys_mmap(16) as *i64 44 sys_wait4(pid, st, 0) 45 if dn >= 0 { sys_close(dn) } 46 let sig: i64 = st[0] & 0x7f 47 if sig != 0 { return 128 + sig } 48 return (st[0] >> 8) & 0xff 49} 50 51func asm_and_run(spath: *u8, elfpath: *u8) -> i64 { 52 let aa: *i64 = sys_mmap(8 * 4) as *i64 53 aa[0] = ASM_TOOL as i64 54 aa[1] = spath as i64 55 aa[2] = elfpath as i64 56 aa[3] = 0 57 let rc_a: i64 = g_run(ASM_TOOL, aa) 58 if rc_a != 0 { return 0 - 200 - rc_a } 59 let rr: *i64 = sys_mmap(8 * 4) as *i64 60 rr[0] = elfpath as i64 61 rr[1] = 0 62 return g_run(elfpath, rr) 63} 64 65func write_shuf_s(path: *u8, sel: i64) -> i64 { 66 let fd: i64 = sys_openat_wr(path, 0x1a4) 67 if fd < 0 { return 0 - 1 } 68 gw(fd, ".text\n" as *u8) 69 gw(fd, "_start:\n" as *u8) 70 gw(fd, "leaq vecS(%rip), %rdi\n" as *u8) 71 gw(fd, "movdqu (%rdi), %xmm0\n" as *u8) 72 gw(fd, "pshufd $" as *u8); gwn(fd, sel); gw(fd, ", %xmm0, %xmm1\n" as *u8) 73 gw(fd, "leaq outbuf(%rip), %rdx\n" as *u8) 74 gw(fd, "movdqu %xmm1, (%rdx)\n" as *u8) 75 gw(fd, "movl (%rdx), %edi\n" as *u8) 76 gw(fd, "movabsq $60, %rax\n" as *u8) 77 gw(fd, "syscall\n" as *u8) 78 gw(fd, ".section .rodata\n" as *u8) 79 gw(fd, "vecS:\n" as *u8) 80 gw(fd, ".byte 11,0,0,0,22,0,0,0,33,0,0,0,44,0,0,0\n" as *u8) 81 gw(fd, ".lcomm outbuf, 16\n" as *u8) 82 sys_close(fd) 83 return 0 84} 85 86func g_emit(fd: i64, pos: i64, neg: i64, ok: i64) -> i64 { 87 gw(fd, "SIMD_VEC_KAT rung=R2R3-3operand+pshufd authored=organ width=128 reg=xmm forms=pshufd(66-0F-70-ib) sovereign(nx_cc->nxasm_x86,no-gcc/qemu/binutils) silicon=real src=[11,22,33,44] pos_sel2=33? " as *u8); gwn(fd, pos) 88 gw(fd, " neg_sel0=11? " as *u8); gwn(fd, neg) 89 gw(fd, " distinct=" as *u8); if pos != neg { gwn(fd, 1) } else { gwn(fd, 0) } 90 if ok == 1 { gw(fd, " verdict=GREEN\n" as *u8) } else { gw(fd, " verdict=RED reason=exit-mismatch-or-3operand-gap\n" as *u8) } 91 return 0 92} 93 94func main() -> i64 { 95 write_shuf_s("/tmp/_sse_shuf_pos.s" as *u8, 2) 96 let pos: i64 = asm_and_run("/tmp/_sse_shuf_pos.s" as *u8, "/tmp/_sse_shuf_pos.elf" as *u8) 97 write_shuf_s("/tmp/_sse_shuf_neg.s" as *u8, 0) 98 let neg: i64 = asm_and_run("/tmp/_sse_shuf_neg.s" as *u8, "/tmp/_sse_shuf_neg.elf" as *u8) 99 100 var ok: i64 = 1 101 if pos != 33 { ok = 0 } 102 if neg != 11 { ok = 0 } 103 if pos == neg { ok = 0 } 104 105 g_emit(1, pos, neg, ok) 106 let lf: i64 = sys_openat_append(SV_LOG, 420) 107 if lf >= 0 { g_emit(lf, pos, neg, ok); sys_close(lf) } 108 // MIGRATED onto nx_gate_verdict by nx_gate_dry_apply (D001, minimal form): every check 109 // row above is untouched, so the PASS/FAIL vector cannot change; only the hand-rolled 110 // verdict emission is replaced by the ONE shared base class. Proven by nx_gate_migrate verify. 111 let ctr__dry: *i64 = gv_ctr() 112 ctr__dry[0] = ok 113 ctr__dry[1] = 1 114 let rc__dry: i64 = gv_verdict("SIMD-SSE-SHUF-GATE" as *u8, ctr__dry, "teeth unchanged; verdict emission migrated onto the shared base class" as *u8) 115 sys_exit(rc__dry) 116 return rc__dry 117}