code wiki / _hdl_build / nx_t4_model_register.nx
`nx_t4_model_register.nx` source

1// nx_t4_model_register.nx -- registers the T4 FIRST REAL MODEL rung through the Librarian's
2// repaired registry (cl_next_idx atomic allocation + cl_register_dual live+journal).
3// ENGINEER evidence = the _t4_first_model_authored gate (O/G/H/I) re-run RIGHT HERE,
4// not asserted: the register refuses unless the gate exits 0 in this very process tree.
5// license_tier: ORIGINAL
6import "nx_cap_register.nx"
7import "nx_capreg_librarian.nx"
8import "nx_syscalls.nx"
9
10func t4r_run(path: *u8) -> i64 {
11    let pid: i64 = sys_fork()
12    if pid == 0 {
13        let dn: i64 = sys_openat_wr("/dev/null" as *u8, 0x1a4)
14        if dn >= 0 { sys_dup3(dn, 1, 0); sys_dup3(dn, 2, 0) }
15        let argv: *i64 = sys_mmap(32) as *i64; argv[0] = path as i64; argv[1] = 0
16        let envp: *i64 = sys_mmap(16) as *i64; envp[0] = 0
17        sys_execve(path, argv, envp); sys_exit(127)
18    }
19    let st: *i64 = sys_mmap(16) as *i64
20    sys_wait4(pid, st, 0)
21    return st[0]
22}
23
24func main() -> i64 {
25    var allok: i64 = 1
26    if t4r_run("/tmp/_t4_first_model_authored.sov.elf" as *u8) != 0 { allok = 0 }
27    cr_w(1, "ENGINEER: T4 first-model gate (O parse-oracle / G XOR / H census 149-149 / I bit-exact) pass=" as *u8); cr_wn(1, allok); cr_w(1, "\n" as *u8)
28    let eng: i64 = ig_engineer(1, 1, 1, allok)
29    let dec: i64 = ig_decision(eng, ig_council(eng, 1, 1, 2), 1)
30    if dec != IG_INGEST { cr_w(1, "HELD\n" as *u8); sys_exit(1) }
31    if cr_can_register(5, 2, 6, dec) != 1 { cr_w(1, "REFUSED\n" as *u8); sys_exit(1) }
32    let lp: *u8 = "/tmp/nishi_cap_registry.log" as *u8
33    let jp: *u8 = "knowledge/status/cap_registry_durable.log" as *u8
34    let idx: i64 = cl_next_idx(lp, jp)
35    let ok: i64 = cl_register_dual(lp, jp, idx, 5,
36        2, "GEN T4-FIRST-MODEL (training-substrate ladder T4; MODELWRIGHT first durable evidence -- the role leaves NO-EVIDENCE). _t4_first_model_authored composes the GATED T6/T5 core (nx_tgrad_core.nx extracted VERBATIM from _tensor_grad_authored; T6 gate re-proven green after extraction) into the team's first REAL trained models, bits-up f32, zero randomness: (1) XOR 2-8-1 relu MLP + gated AdamW, deterministic symmetry-breaking init (fixed pattern table closes the documented zero-init relu trap; principled-init research row stays open) -- loss 0-milli, 4/4 preds; (2) REAL-DATA 8-way service classifier on the elder census (149 services, first-8-bytes centered features -> svc/gen/data/orch/worker/mon/util/other) trained to 149/149 = 100 percent with per-class predicted counts == ground truth. GATES: O census-parse == the file's own CENSUS-SUM line (data oracle); G XOR; H census 100 percent; I BIT-EXACT two-run training both lanes (33+416 weight cells identical -- the standing EXCEED axis at every rung); TAMPER RUN proves RED (corrupted class token -> GATE O FAIL exit 1). FIVE MEASURED training-dynamics lessons banked in-source: per-sample SGD plateaus 141/149; per-sample Adam COLLAPSES to the 88-sample majority; unweighted full-batch leaves exactly the rarest classes wrong (util+mon) -> inverse-frequency class weights from the parsed histogram; uncentered all-positive byte features freeze relu nets across THREE optimizers -> center at 84/32; post-convergence constant-lr Adam BLOWS UP (grads->0 => v->0 => mh/eps spike jumps basins) -> deterministic early-stop at convergence (ep 464). Evidence: knowledge/status/modelwright.log (loss curves + verdicts, scorecard-wired -> MODELWRIGHT=FUNCTIONAL). NEXT: T4b closed-loop (train on the synthesis corpus = team-generated gate-verified data), T2 tokenizer" as *u8)
37    if ok != 1 { cr_w(1, "DUAL-WRITE FAILED\n" as *u8); sys_exit(1) }
38    cr_w(1, "CAPREG idx=" as *u8); cr_wn(1, idx); cr_w(1, " REGISTERED via Librarian alloc+dual-write (T4 first model)\n" as *u8)
39    sys_exit(0)
40    return 0
41}
nx_t4_model_register.nx source

`nx_t4_model_register.nx` source
