`nx_x86.nx` source

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1// nx_x86.nx -- Implements a 16-bit real-mode x86 CPU skeleton for running COM-style programs and DOS interrupts.
2const O_MAGIC_65536: i64 = 65536
3const O_MAGIC_65535: i64 = 65535
4// nx_x86.nx -- R1.0a SOVEREIGN x86 16-bit real-mode CPU skeleton (the start of the DOS target). Same proven
5// substrate as nx_chip8: fixed-offset base-relative state (runs native + wasm), fetch-decode-execute. This
6// rung covers a REAL register/immediate/jump subset (enough for a .COM-style countdown/branch program);
7// ModR/M memory operands, segmentation (seg*16+off), and BIOS/DOS INTs are the next rungs. Proven vs a
8// DOSBox/qemu oracle later (3rd-party-proving for the standard ISA). license_tier: ORIGINAL
9//
10// genealogy_id: sovereign_emulator_x86   lineage_id: nx_x86_v1  (parents: nx_chip8 fetch-decode-execute idiom)
11//
12// 16-bit GP regs in x86 opcode order: 0=AX 1=CX 2=DX 3=BX 4=SP 5=BP 6=SI 7=DI. COM model: one 64 KiB segment,
13// program loads at IP=0x100. Flags tracked: ZF, CF, SF.
14const O_MEM:   i64 = 0          // 65536 guest bytes (one real-mode segment)
15const O_REGS:  i64 = 65536      // 8 GP regs (i64, hold 16-bit values) -> 65600
16const O_IP:    i64 = 65600
17const O_ZF:    i64 = 65608
18const O_CF:    i64 = 65616
19const O_SF:    i64 = 65624
20const O_MM:    i64 = 65632      // 4-i64 ModR/M decode scratch (reg, is_reg, ea) -- avoids per-step alloc
21const O_CON:     i64 = 65664    // 4096-byte console output buffer (DOS INT 21h writes here)
22const O_CON_LEN: i64 = 69760    // console length cursor
23const O_EXIT:    i64 = 69768    // set by INT 21h AH=4Ch (program terminate)
24const O_FSNAME:  i64 = 69776    // Nishi-DOS sovereign FS: one file's name (ASCIIZ)
25const O_FSLEN:   i64 = 69792    // its byte length
26const O_FSDATA:  i64 = 69800    // its bytes (up to 4096)
27const O_HOPEN:   i64 = 73896    // 8 file-handle open flags
28const O_HPOS:    i64 = 73960    // 8 file-handle byte positions
29
30func x86_reset(base: i64) -> i64 {
  let mem: *u8 = (base + O_MEM) as *u8
  var i: i64 = 0
  while i < O_MAGIC_65536 { mem[i] = 0 as u8; i = i + 1 }
  let regs: *i64 = (base + O_REGS) as *i64
  i = 0; while i < 8 { regs[i] = 0; i = i + 1 }
  let ipp: *i64 = (base + O_IP) as *i64
  ipp[0] = 256            // 0x100 -- COM entry
  let z: *i64 = (base + O_ZF) as *i64; z[0] = 0
  let c: *i64 = (base + O_CF) as *i64; c[0] = 0
  let s: *i64 = (base + O_SF) as *i64; s[0] = 0
  let cl: *i64 = (base + O_CON_LEN) as *i64; cl[0] = 0
  let ex: *i64 = (base + O_EXIT) as *i64; ex[0] = 0
  let flz: *i64 = (base + O_FSLEN) as *i64; flz[0] = 0
  let hoz: *i64 = (base + O_HOPEN) as *i64
  var hz: i64 = 0
  while hz < 8 { hoz[hz] = 0; hz = hz + 1 }
  return 0
48}
49func x86_load(base: i64, addr: i64, byte: i64) -> i64 {
  let mem: *u8 = (base + O_MEM) as *u8
  mem[addr] = (byte & 0xff) as u8
  return 0
53}
54
55// set ZF + SF from a 16-bit result (CF is set per-opcode by the caller).
56func x86_setzsf(base: i64, res: i64) -> i64 {
  let z: *i64 = (base + O_ZF) as *i64
  let s: *i64 = (base + O_SF) as *i64
  if (res & 0xffff) == 0 { z[0] = 1 } else { z[0] = 0 }
  s[0] = (res >> 15) & 1
  return 0
62}
63
64// ---- ModR/M (16-bit) + memory operands ----
65func x86_rd16(base: i64, ea: i64) -> i64 {
  let mem: *u8 = (base + O_MEM) as *u8
  return (mem[ea & 0xffff] as i64) | ((mem[(ea + 1) & 0xffff] as i64) << 8)
68}
69func x86_wr16(base: i64, ea: i64, v: i64) -> i64 {
  let mem: *u8 = (base + O_MEM) as *u8
  mem[ea & 0xffff] = (v & 0xff) as u8
  mem[(ea + 1) & 0xffff] = ((v >> 8) & 0xff) as u8
  return 0
74}
75func x86_peek16(base: i64, addr: i64) -> i64 { return x86_rd16(base, addr) }   // gate/IO read
76
77// decode ModR/M (+disp) at ip: mm[0]=reg field, mm[1]=is_register(1/0), mm[2]=reg index OR effective address.
78// returns the new ip. The 8 16-bit addressing modes, incl the rm=6 disp16(mod0) vs [BP+disp](mod1,2) quirk.
79func x86_modrm(base: i64, ip: i64, mm: *i64) -> i64 {
  let mem: *u8 = (base + O_MEM) as *u8
  let regs: *i64 = (base + O_REGS) as *i64
  let modrm: i64 = mem[ip] as i64
  var p: i64 = ip + 1
  let md: i64 = (modrm >> 6) & 3
  mm[0] = (modrm >> 3) & 7
  let rm: i64 = modrm & 7
  if md == 3 { mm[1] = 1; mm[2] = rm; return p }
  mm[1] = 0
  var ea: i64 = 0
  if rm == 0 { ea = regs[3] + regs[6] }                       // BX+SI
  if rm == 1 { ea = regs[3] + regs[7] }                       // BX+DI
  if rm == 2 { ea = regs[5] + regs[6] }                       // BP+SI
  if rm == 3 { ea = regs[5] + regs[7] }                       // BP+DI
  if rm == 4 { ea = regs[6] }                                 // SI
  if rm == 5 { ea = regs[7] }                                 // DI
  if rm == 6 { if md == 0 { ea = 0 } else { ea = regs[5] } }  // disp16 (mod0) / BP (mod1,2)
  if rm == 7 { ea = regs[3] }                                 // BX
  if md == 1 {
      var d8: i64 = mem[p] as i64
      if d8 >= 128 { d8 = d8 - 256 }
      p = p + 1
      ea = ea + d8
  }
  if md == 2 {
      let d16: i64 = (mem[p] as i64) | ((mem[p + 1] as i64) << 8)
      p = p + 2
      ea = ea + d16
  }
  if md == 0 { if rm == 6 {
      let d16b: i64 = (mem[p] as i64) | ((mem[p + 1] as i64) << 8)
      p = p + 2
      ea = ea + d16b
  } }
  mm[2] = ea & 0xffff
  return p
116}
117func x86_rm_get(base: i64, mm: *i64) -> i64 {
  if mm[1] == 1 { let regs: *i64 = (base + O_REGS) as *i64; return regs[mm[2]] }
  return x86_rd16(base, mm[2])
120}
121func x86_rm_set(base: i64, mm: *i64, v: i64) -> i64 {
  if mm[1] == 1 { let regs: *i64 = (base + O_REGS) as *i64; regs[mm[2]] = v & 0xffff; return 0 }
  x86_wr16(base, mm[2], v & 0xffff)
  return 0
125}
126
127// ---- 8-bit registers (AL/CL/DL/BL = r<4 low byte ; AH/CH/DH/BH = r>=4 high byte of regs[r-4]) ----
128func x86_set_r8(base: i64, r: i64, v: i64) -> i64 {
  let regs: *i64 = (base + O_REGS) as *i64
  if r < 4 { regs[r] = (regs[r] & 0xff00) | (v & 0xff) }
  else { regs[r - 4] = (regs[r - 4] & 0xff) | ((v & 0xff) << 8) }
  return 0
133}
134
135// ---- Nishi-DOS sovereign virtual FS (R-DOS1): one host-loaded file (name + bytes) ----
136func x86_fs_put(base: i64, name: *u8, data: *u8, len: i64) -> i64 {
  let fsname: *u8 = (base + O_FSNAME) as *u8
  var i: i64 = 0
  while name[i] != (0 as u8) { fsname[i] = name[i]; i = i + 1 }
  fsname[i] = 0 as u8
  let fsdata: *u8 = (base + O_FSDATA) as *u8
  i = 0
  while i < len { fsdata[i] = data[i]; i = i + 1 }
  let fl: *i64 = (base + O_FSLEN) as *i64
  fl[0] = len
  return 0
147}
148// is the guest ASCIIZ filename at mem[off..] equal to the FS file's name?
149func x86_fs_nameeq(base: i64, off: i64) -> i64 {
  let mem: *u8 = (base + O_MEM) as *u8
  let fsname: *u8 = (base + O_FSNAME) as *u8
  var i: i64 = 0
  while 1 == 1 {
      let a: i64 = mem[(off + i) & 0xffff] as i64
      let b: i64 = fsname[i] as i64
      if a != b { return 0 }
      if a == 0 { return 1 }
      i = i + 1
  }
  return 0
161}
162
163// ---- HLE Nishi-DOS INT 21h: print (09/02), terminate (4C), open/read/close (3D/3F/3E, R-DOS1) ----
164func x86_dos_int21(base: i64) -> i64 {
  let regs: *i64 = (base + O_REGS) as *i64
  let mem: *u8 = (base + O_MEM) as *u8
  let con: *u8 = (base + O_CON) as *u8
  let clen: *i64 = (base + O_CON_LEN) as *i64
  let ah: i64 = (regs[0] >> 8) & 0xff
  if ah == 9 {                                // print $-terminated string at DS:DX (DS=0 in COM)
      var off: i64 = regs[2] & 0xffff
      var guard: i64 = 0
      while guard < O_MAGIC_65536 {
          let ch: i64 = mem[off] as i64
          if ch == 36 { break }               // '$'
          con[clen[0]] = ch as u8
          clen[0] = clen[0] + 1
          off = (off + 1) & 0xffff
          guard = guard + 1
      }
  }
  if ah == 2 {                                // print char in DL
      con[clen[0]] = (regs[2] & 0xff) as u8
      clen[0] = clen[0] + 1
  }
  if ah == 61 {                               // 3Dh open existing file (DS:DX = ASCIIZ name) -> AX=handle
      let dx: i64 = regs[2] & 0xffff
      let cf: *i64 = (base + O_CF) as *i64
      if x86_fs_nameeq(base, dx) == 1 {
          let hopen: *i64 = (base + O_HOPEN) as *i64
          let hpos: *i64 = (base + O_HPOS) as *i64
          var h: i64 = 5                       // 0-4 reserved (stdin/out/err/aux/prn)
          while h < 8 { if hopen[h] == 0 { break } h = h + 1 }
          hopen[h] = 1
          hpos[h] = 0
          regs[0] = h
          cf[0] = 0
      } else {
          regs[0] = 2                          // ENOENT
          cf[0] = 1
      }
  }
  if ah == 63 {                               // 3Fh read (BX=handle, CX=count, DS:DX=buf) -> AX=bytes read
      let bx: i64 = regs[3] & 0xffff
      let cx: i64 = regs[1] & 0xffff
      let dx: i64 = regs[2] & 0xffff
      let hpos: *i64 = (base + O_HPOS) as *i64
      let fl: *i64 = (base + O_FSLEN) as *i64
      let fsdata: *u8 = (base + O_FSDATA) as *u8
      let gmem: *u8 = (base + O_MEM) as *u8
      var n: i64 = cx
      let avail: i64 = fl[0] - hpos[bx]
      if n > avail { n = avail }
      var i: i64 = 0
      while i < n { gmem[(dx + i) & 0xffff] = fsdata[hpos[bx] + i]; i = i + 1 }
      hpos[bx] = hpos[bx] + n
      regs[0] = n
  }
  if ah == 62 {                               // 3Eh close (BX=handle)
      let bx: i64 = regs[3] & 0xffff
      let hopen: *i64 = (base + O_HOPEN) as *i64
      hopen[bx] = 0
  }
  if ah == 76 {                               // 4Ch terminate
      let ex: *i64 = (base + O_EXIT) as *i64
      ex[0] = 1
  }
  return 0
229}
230func x86_con_len(base: i64) -> i64 { let c: *i64 = (base + O_CON_LEN) as *i64; return c[0] }
231func x86_con_byte(base: i64, i: i64) -> i64 { let con: *u8 = (base + O_CON) as *u8; return con[i] as i64 }
232
233// execute ONE instruction. returns 0 normally, 1 on HLT (IP left on the HLT byte).
234func x86_step(base: i64) -> i64 {
  let mem: *u8 = (base + O_MEM) as *u8
  let regs: *i64 = (base + O_REGS) as *i64
  let ipp: *i64 = (base + O_IP) as *i64
  let zf: *i64 = (base + O_ZF) as *i64
  let cf: *i64 = (base + O_CF) as *i64
  let mm: *i64 = (base + O_MM) as *i64
241
  var ip: i64 = ipp[0]
  let op: i64 = mem[ip] as i64
  ip = ip + 1
245
  var halt: i64 = 0
247
  // MOV r16, imm16  (B8+r)
  if op >= 184 { if op <= 191 {
      let r: i64 = op - 184
      let imm: i64 = (mem[ip] as i64) | ((mem[ip + 1] as i64) << 8)
      ip = ip + 2
      regs[r] = imm & 0xffff
  } }
  // INC r16  (40+r) -- affects ZF,SF not CF
  if op >= 64 { if op <= 71 {
      let r: i64 = op - 64
      let res: i64 = (regs[r] + 1) & 0xffff
      regs[r] = res
      x86_setzsf(base, res)
  } }
  // DEC r16  (48+r) -- affects ZF,SF not CF
  if op >= 72 { if op <= 79 {
      let r: i64 = op - 72
      let res: i64 = (regs[r] - 1) & 0xffff
      regs[r] = res
      x86_setzsf(base, res)
  } }
  // ADD AX, imm16  (05)
  if op == 5 {
      let imm: i64 = (mem[ip] as i64) | ((mem[ip + 1] as i64) << 8)
      ip = ip + 2
      let res: i64 = regs[0] + imm
      if res > O_MAGIC_65535 { cf[0] = 1 } else { cf[0] = 0 }
      regs[0] = res & 0xffff
      x86_setzsf(base, regs[0])
  }
  // SUB AX, imm16  (2D)
  if op == 45 {
      let imm: i64 = (mem[ip] as i64) | ((mem[ip + 1] as i64) << 8)
      ip = ip + 2
      let a: i64 = regs[0]
      if a < imm { cf[0] = 1 } else { cf[0] = 0 }
      regs[0] = (a - imm) & 0xffff
      x86_setzsf(base, regs[0])
  }
  // CMP AX, imm16  (3D) -- sub, set flags, discard result
  if op == 61 {
      let imm: i64 = (mem[ip] as i64) | ((mem[ip + 1] as i64) << 8)
      ip = ip + 2
      let a: i64 = regs[0]
      if a < imm { cf[0] = 1 } else { cf[0] = 0 }
      x86_setzsf(base, (a - imm) & 0xffff)
  }
  // JMP short rel8  (EB)
  if op == 235 {
      var rel: i64 = mem[ip] as i64
      if rel >= 128 { rel = rel - 256 }
      ip = ip + 1
      ip = ip + rel
  }
  // JZ/JE rel8 (74) ; JNZ/JNE rel8 (75)
  if op == 116 {
      var rel: i64 = mem[ip] as i64
      if rel >= 128 { rel = rel - 256 }
      ip = ip + 1
      if zf[0] == 1 { ip = ip + rel }
  }
  if op == 117 {
      var rel: i64 = mem[ip] as i64
      if rel >= 128 { rel = rel - 256 }
      ip = ip + 1
      if zf[0] == 0 { ip = ip + rel }
  }
  // NOP (90)
  if op == 144 { }
  // HLT (F4) -- leave IP on the HLT byte, signal halt
  if op == 244 { ip = ip - 1; halt = 1 }
319
  // ---- ModR/M memory-operand opcodes (16-bit) ----
  if op == 137 {                              // 89 /r  MOV r/m16, r16
      ip = x86_modrm(base, ip, mm)
      x86_rm_set(base, mm, regs[mm[0]])
  }
  if op == 139 {                              // 8B /r  MOV r16, r/m16
      ip = x86_modrm(base, ip, mm)
      regs[mm[0]] = x86_rm_get(base, mm) & 0xffff
  }
  if op == 1 {                                // 01 /r  ADD r/m16, r16
      ip = x86_modrm(base, ip, mm)
      let a1: i64 = x86_rm_get(base, mm)
      let r1: i64 = a1 + regs[mm[0]]
      if r1 > O_MAGIC_65535 { cf[0] = 1 } else { cf[0] = 0 }
      x86_rm_set(base, mm, r1)
      x86_setzsf(base, r1 & 0xffff)
  }
  if op == 3 {                                // 03 /r  ADD r16, r/m16
      ip = x86_modrm(base, ip, mm)
      let r2: i64 = regs[mm[0]] + x86_rm_get(base, mm)
      if r2 > O_MAGIC_65535 { cf[0] = 1 } else { cf[0] = 0 }
      regs[mm[0]] = r2 & 0xffff
      x86_setzsf(base, regs[mm[0]])
  }
  if op == 41 {                               // 29 /r  SUB r/m16, r16
      ip = x86_modrm(base, ip, mm)
      let a3: i64 = x86_rm_get(base, mm)
      let b3: i64 = regs[mm[0]]
      if a3 < b3 { cf[0] = 1 } else { cf[0] = 0 }
      x86_rm_set(base, mm, (a3 - b3) & 0xffff)
      x86_setzsf(base, (a3 - b3) & 0xffff)
  }
  if op == 57 {                               // 39 /r  CMP r/m16, r16
      ip = x86_modrm(base, ip, mm)
      let a4: i64 = x86_rm_get(base, mm)
      let b4: i64 = regs[mm[0]]
      if a4 < b4 { cf[0] = 1 } else { cf[0] = 0 }
      x86_setzsf(base, (a4 - b4) & 0xffff)
  }
  if op == 49 {                               // 31 /r  XOR r/m16, r16
      ip = x86_modrm(base, ip, mm)
      let r5: i64 = (x86_rm_get(base, mm) ^ regs[mm[0]]) & 0xffff
      cf[0] = 0
      x86_rm_set(base, mm, r5)
      x86_setzsf(base, r5)
  }
  if op == 199 {                              // C7 /0  MOV r/m16, imm16
      ip = x86_modrm(base, ip, mm)
      let imm7: i64 = (mem[ip] as i64) | ((mem[ip + 1] as i64) << 8)
      ip = ip + 2
      x86_rm_set(base, mm, imm7 & 0xffff)
  }
  // MOV r8, imm8  (B0+r)
  if op >= 176 { if op <= 183 {
      let imm8: i64 = mem[ip] as i64
      ip = ip + 1
      x86_set_r8(base, op - 176, imm8)
  } }
  // INT imm8  (CD) -- high-level: INT 21h -> the DOS handler; AH=4Ch sets the exit flag -> halt
  if op == 205 {
      let n: i64 = mem[ip] as i64
      ip = ip + 1
      if n == 33 { x86_dos_int21(base) }
      let exitp: *i64 = (base + O_EXIT) as *i64
      if exitp[0] == 1 { halt = 1 }
  }
386
  ipp[0] = ip & 0xffff
  return halt
389}
390
391// run until HLT or a step cap (cap guards against runaway loops). returns steps executed.
392func x86_run(base: i64, cap: i64) -> i64 {
  var c: i64 = 0
  while c < cap {
      if x86_step(base) == 1 { return c + 1 }
      c = c + 1
  }
  return c
399}
400
401func x86_reg(base: i64, r: i64) -> i64 { let regs: *i64 = (base + O_REGS) as *i64; return regs[r & 7] }
402func x86_ip(base: i64) -> i64 { let ipp: *i64 = (base + O_IP) as *i64; return ipp[0] }
403func x86_zf(base: i64) -> i64 { let z: *i64 = (base + O_ZF) as *i64; return z[0] }
404func x86_cf(base: i64) -> i64 { let c: *i64 = (base + O_CF) as *i64; return c[0] }
405func x86_sf(base: i64) -> i64 { let s: *i64 = (base + O_SF) as *i64; return s[0] }
nx_x86.nx source

`nx_x86.nx` source
