`nxasm_v2.nx` source

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1// nxasm_v2.nx -- the Nishi RV64 assembler, with labels + directives.
2//
3// Complete enough to assemble the .s files nxc2 emits for small
4// programs.  Two-pass:
5//   Pass 1: walk tokens, record labels and their addresses.
6//   Pass 2: walk tokens, emit bytes to output buffer.
7//
8// Supports:
9//   * Mnemonics: li, mv, ret, ecall, ld, sd, add, sub, addi, jalr
10//     plus branches / jumps with label operands: j, jal, call, tail,
11//     bnez, beqz.
12//   * Directives: .text, .globl, .type, .size, .attribute, .option,
13//     .section, .asciz, .byte.  First four are ignored (metadata).
14//   * Labels: `name:` at line start; referenced by jumps.
15//
16// Output is a raw byte buffer of code + rodata.  An ELF wrapper
17// layer (see elf_writer.nx) adds headers to make it runnable.
18
19// Stderr logging routes through sys_write -- pull in the RV64 syscall
20// vocabulary that the assembler will run under (it produces RV64 ELFs
21// and is itself expected to execute on RV64 targets).
22import "../runtime/nx_syscalls.nx"
23
24// ===== encoder =====================================================
25
26func enc_r(opcode: i64, funct3: i64, funct7: i64,
         rd: i64, rs1: i64, rs2: i64) -> i64 {
  return (funct7 << 25) | (rs2 << 20) | (rs1 << 15)
       | (funct3 << 12) | (rd  <<  7) | opcode
30}
31
32func enc_i(opcode: i64, funct3: i64,
         rd: i64, rs1: i64, imm: i64) -> i64 {
  let imm12: i64 = imm & 0xFFF
  return (imm12 << 20) | (rs1 << 15) | (funct3 << 12)
       | (rd << 7) | opcode
37}
38
39func enc_s(opcode: i64, funct3: i64,
         rs1: i64, rs2: i64, imm: i64) -> i64 {
  let hi: i64 = (imm >> 5) & 0x7F
  let lo: i64 =  imm       & 0x1F
  return (hi << 25) | (rs2 << 20) | (rs1 << 15)
       | (funct3 << 12) | (lo << 7) | opcode
45}
46
47func enc_u(opcode: i64, rd: i64, imm20: i64) -> i64 {
  return ((imm20 & 0xFFFFF) << 12) | (rd << 7) | opcode
49}
50
51// J-type with bit-scrambled 21-bit signed offset.
52func enc_j(opcode: i64, rd: i64, imm: i64) -> i64 {
  let b20:    i64 = (imm >> 20) & 1
  let b10_1:  i64 = (imm >> 1)  & 0x3FF
  let b11:    i64 = (imm >> 11) & 1
  let b19_12: i64 = (imm >> 12) & 0xFF
  return (b20 << 31) | (b10_1 << 21) | (b11 << 20)
       | (b19_12 << 12) | (rd << 7) | opcode
59}
60
61// B-type 13-bit signed offset.
62func enc_b(opcode: i64, funct3: i64,
         rs1: i64, rs2: i64, imm: i64) -> i64 {
  let b12:    i64 = (imm >> 12) & 1
  let b10_5:  i64 = (imm >> 5)  & 0x3F
  let b4_1:   i64 = (imm >> 1)  & 0xF
  let b11:    i64 = (imm >> 11) & 1
  return (b12 << 31) | (b10_5 << 25) | (rs2 << 20) | (rs1 << 15)
       | (funct3 << 12) | (b4_1 << 8) | (b11 << 7) | opcode
70}
71
72// ===== tokens =======================================================
73
74struct AsmTok {
  kind:  i64,
  val:   i64,
  start: i64,
  len:   i64,
79}
80
81func asm_is_alpha(c: i64) -> i64 {
  if c >= 0x41 { if c <= 0x5A { return 1 } }
  if c >= 0x61 { if c <= 0x7A { return 1 } }
  if c == 0x5F { return 1 }
  if c == 0x2E { return 1 }
  return 0
87}
88func asm_is_digit(c: i64) -> i64 {
  if c >= 0x30 { if c <= 0x39 { return 1 } }
  return 0
91}
92func is_hex(c: i64) -> i64 {
  if asm_is_digit(c) { return 1 }
  if c >= 0x41 { if c <= 0x46 { return 1 } }
  if c >= 0x61 { if c <= 0x66 { return 1 } }
  return 0
97}
98func hexv(c: i64) -> i64 {
  if c >= 0x30 { if c <= 0x39 { return c - 0x30 } }
  if c >= 0x41 { if c <= 0x46 { return c - 0x37 } }
  if c >= 0x61 { if c <= 0x66 { return c - 0x57 } }
  return 0
103}
104func is_space(c: i64) -> i64 {
  if c == 0x20 { return 1 }
  if c == 0x09 { return 1 }
  if c == 0x0A { return 1 }
  if c == 0x0D { return 1 }
  return 0
110}
111
112func lex_one(src: *u8, pos: i64, len: i64, out: *AsmTok) -> i64 {
  var done_ws: i64 = 0
  while done_ws == 0 {
      if pos >= len { done_ws = 1 }
      if done_ws == 0 {
          let c: i64 = src[pos]
          if is_space(c) { pos = pos + 1 }
          if is_space(c) == 0 {
              if c == 0x23 {
                  var nl: i64 = 0
                  while nl == 0 {
                      if pos >= len { nl = 1 }
                      if nl == 0 {
                          if src[pos] == 0x0A { pos = pos + 1; nl = 1 }
                          if nl == 0 { pos = pos + 1 }
                      }
                  }
              }
              if c != 0x23 { done_ws = 1 }
          }
      }
  }
  if pos >= len {
      out.kind = 0; out.start = pos; out.len = 0; out.val = 0
      return pos
  }
  let c0: i64 = src[pos]
  var sign: i64 = 1
  if c0 == 0x2D {
      if pos + 1 < len {
          if asm_is_digit(src[pos + 1]) { sign = -1; pos = pos + 1 }
      }
  }
  let c1: i64 = src[pos]
  if asm_is_digit(c1) {
      var v: i64 = 0
      let s: i64 = pos
      if c1 == 0x30 {
          if pos + 1 < len {
              if src[pos + 1] == 0x78 {
                  pos = pos + 2
                  while pos < len {
                      let d: i64 = src[pos]
                      if is_hex(d) == 0 { break }
                      v = (v << 4) | hexv(d)
                      pos = pos + 1
                  }
                  out.kind = 2; out.val = v * sign; out.start = s; out.len = pos - s
                  return pos
              }
          }
      }
      while pos < len {
          let d: i64 = src[pos]
          if asm_is_digit(d) == 0 { break }
          v = v * 10 + (d - 0x30)
          pos = pos + 1
      }
      out.kind = 2; out.val = v * sign; out.start = s; out.len = pos - s
      return pos
  }
  if asm_is_alpha(c1) {
      let s: i64 = pos
      pos = pos + 1
      while pos < len {
          let d: i64 = src[pos]
          if asm_is_alpha(d) == 0 {
              if asm_is_digit(d) == 0 { break }
          }
          pos = pos + 1
      }
      out.kind = 1; out.val = pos - s; out.start = s; out.len = pos - s
      return pos
  }
  if c1 == 0x22 {
      let s: i64 = pos
      pos = pos + 1
      while pos < len {
          if src[pos] == 0x22 { break }
          pos = pos + 1
      }
      if pos < len { pos = pos + 1 }
      out.kind = 4; out.val = pos - s; out.start = s; out.len = pos - s
      return pos
  }
  out.kind = 3; out.val = c1; out.start = pos; out.len = 1
  return pos + 1
199}
200
201// ===== register-name lookup ========================================
202
203func s_eq2(src: *u8, off: i64, len: i64, a: i64, b: i64) -> i64 {
  if len != 2 { return 0 }
  if src[off]     != a { return 0 }
  if src[off + 1] != b { return 0 }
  return 1
208}
209func s_eq3(src: *u8, off: i64, len: i64, a: i64, b: i64, c: i64) -> i64 {
  if len != 3 { return 0 }
  if src[off]     != a { return 0 }
  if src[off + 1] != b { return 0 }
  if src[off + 2] != c { return 0 }
  return 1
215}
216func s_eq4(src: *u8, off: i64, len: i64, a: i64, b: i64, c: i64, d: i64) -> i64 {
  if len != 4 { return 0 }
  if src[off]     != a { return 0 }
  if src[off + 1] != b { return 0 }
  if src[off + 2] != c { return 0 }
  if src[off + 3] != d { return 0 }
  return 1
223}
224func s_eq5(src: *u8, off: i64, len: i64, a: i64, b: i64, c: i64, d: i64, e: i64) -> i64 {
  if len != 5 { return 0 }
  if src[off]     != a { return 0 }
  if src[off + 1] != b { return 0 }
  if src[off + 2] != c { return 0 }
  if src[off + 3] != d { return 0 }
  if src[off + 4] != e { return 0 }
  return 1
232}
233// Was: s_eq6(src, off, len, a, b, c, d, e, f) -- 9 args.  The
234// self-host compiler's Instr struct only has 8 inline operand slots
235// (op0..op7); a 9-arg call falls through to bogus `mv a8, ...`
236// emission at codegen time (a8 isn't a real RV64 register).  Blocked
237// Wheeler DDC self-self compile until refactored.  2026-05-16 fix:
238// take the 6 bytes as a string pointer + length so the call is 5
239// args, well under the ABI limit.  Caller passes a string literal
240// like ".asciz" instead of 6 char codes.
241func s_eq6(src: *u8, off: i64, len: i64, pat: *u8, plen: i64) -> i64 {
  if len != plen { return 0 }
  var i: i64 = 0
  while i < plen {
      if src[off + i] != pat[i] { return 0 }
      i = i + 1
  }
  return 1
249}
250
251func reg_lookup(src: *u8, off: i64, len: i64) -> i64 {
  if len == 2 {
      let a: i64 = src[off]
      let b: i64 = src[off + 1]
      if a == 0x61 { if b >= 0x30 { if b <= 0x37 { return 10 + (b - 0x30) } } }
      if a == 0x74 {
          if b >= 0x30 { if b <= 0x32 { return 5 + (b - 0x30) } }
          if b >= 0x33 { if b <= 0x36 { return 28 + (b - 0x33) } }
      }
      if a == 0x73 {
          if b == 0x30 { return 8 }
          if b == 0x31 { return 9 }
          if b >= 0x32 { if b <= 0x39 { return 18 + (b - 0x32) } }
          if b == 0x70 { return 2 }
      }
      // Raw x-form: x0..x9 (Task #37).  Kernel trap.S uses these
      // directly instead of ABI names.  Without this branch nxasm
      // bails on `sd x1, 0(sp)` with misleading "bad mnemonic 'sd'".
      if a == 0x78 { if b >= 0x30 { if b <= 0x39 { return b - 0x30 } } }
      if s_eq2(src, off, len, 0x72, 0x61) { return 1 }
      if s_eq2(src, off, len, 0x67, 0x70) { return 3 }
      if s_eq2(src, off, len, 0x74, 0x70) { return 4 }
      if s_eq2(src, off, len, 0x66, 0x70) { return 8 }
  }
  if len == 3 {
      if s_eq3(src, off, len, 0x73, 0x31, 0x30) { return 26 }
      if s_eq3(src, off, len, 0x73, 0x31, 0x31) { return 27 }
      // Raw x-form: x10..x31 (Task #37).
      let a3: i64 = src[off]
      let b3: i64 = src[off + 1]
      let c3: i64 = src[off + 2]
      if a3 == 0x78 {
          if b3 == 0x31 {                        // x10..x19
              if c3 >= 0x30 { if c3 <= 0x39 { return 10 + (c3 - 0x30) } }
          }
          if b3 == 0x32 {                        // x20..x29
              if c3 >= 0x30 { if c3 <= 0x39 { return 20 + (c3 - 0x30) } }
          }
          if b3 == 0x33 {                        // x30, x31
              if c3 == 0x30 { return 30 }
              if c3 == 0x31 { return 31 }
          }
      }
  }
  if len == 4 {
      if s_eq4(src, off, len, 0x7A, 0x65, 0x72, 0x6F) { return 0 }
  }
  return -1
299}
300
301// ===== label table =================================================
302//
303// Label array.  The assembler walks tokens twice; pass 1 fills the
304// table with (name, addr), pass 2 consults it for offset resolution.
305
306struct Label {
  name_start: i64,
  name_len:   i64,
  addr:       i64,
  defined:    i64,
311}
312
313struct Asm {
  src:      *u8,
  src_len:  i64,
  pos:      i64,    // token cursor
  cur_addr: i64,    // address in the text section as we emit
  pass:     i64,    // 1 or 2
  out:      *u8,    // output byte buffer (pass 2)
  out_pos:  i64,    // next byte to write
  labels:   *Label,
  n_labels: i64,
323}
324
325func label_eq(src: *u8, a_off: i64, a_len: i64,
            b_off: i64, b_len: i64) -> i64 {
  if a_len != b_len { return 0 }
  var i: i64 = 0
  while i < a_len {
      if src[a_off + i] != src[b_off + i] { return 0 }
      i = i + 1
  }
  return 1
334}
335
336// Find a label by name; returns index or -1.
337func label_find(A: *Asm, name_off: i64, name_len: i64) -> i64 {
  var i: i64 = 0
  let base: i64 = A.labels as i64
  while i < A.n_labels {
      let lab: *Label = (base + i * 32) as *Label
      if label_eq(A.src, lab.name_start, lab.name_len, name_off, name_len) {
          return i
      }
      i = i + 1
  }
  return -1
348}
349
350// Define a label at the current address.
351// Bounds-checked against the pool size set in `assemble`.  If we
352// overflow, print a loud message + return -1 so the caller can decide
353// (today: assemble_pass treats <0 as fatal).
354const LABELS_CAP: i64 = 8192
355
356func label_define(A: *Asm, name_off: i64, name_len: i64) -> i64 {
  let idx: i64 = A.n_labels
  if idx >= LABELS_CAP {
      sys_write(2, "nxasm: label pool overflow (cap=" as *u8, 32)
      sys_write(2, "8192)\n" as *u8, 6)
      return -1
  }
  let base: i64 = A.labels as i64
  let lab: *Label = (base + idx * 32) as *Label
  lab.name_start = name_off
  lab.name_len   = name_len
  lab.addr       = A.cur_addr
  lab.defined    = 1
  A.n_labels = idx + 1
  return idx
371}
372
373// ===== byte emission helpers (pass 2 only) ==========================
374
375func emit_u32(A: *Asm, v: i64) -> i64 {
  if A.pass == 2 {
      let out: *u8 = A.out
      let p: i64 = A.out_pos
      out[p]     = v & 0xFF
      out[p + 1] = (v >> 8)  & 0xFF
      out[p + 2] = (v >> 16) & 0xFF
      out[p + 3] = (v >> 24) & 0xFF
      A.out_pos = p + 4
  }
  A.cur_addr = A.cur_addr + 4
  return 0
387}
388
389func emit_byte(A: *Asm, v: i64) -> i64 {
  if A.pass == 2 {
      let out: *u8 = A.out
      let p: i64 = A.out_pos
      out[p] = v & 0xFF
      A.out_pos = p + 1
  }
  A.cur_addr = A.cur_addr + 1
  return 0
398}
399
400// ===== parser helpers =============================================
401
402func next_tok(A: *Asm, t: *AsmTok) -> i64 {
  A.pos = lex_one(A.src, A.pos, A.src_len, t)
  return A.pos
405}
406func expect_punct(A: *Asm, t: *AsmTok, c: i64) -> i64 {
  next_tok(A, t)
  if t.kind != 3 { return 1 }
  if t.val != c  { return 2 }
  return 0
411}
412func expect_reg(A: *Asm, t: *AsmTok) -> i64 {
  next_tok(A, t)
  if t.kind != 1 { return -1 }
  return reg_lookup(A.src, t.start, t.len)
416}
417func expect_int(A: *Asm, t: *AsmTok, err: *i64) -> i64 {
  next_tok(A, t)
  if t.kind != 2 {
      *err = 1
      return 0
  }
  *err = 0
  return t.val
425}
426
427// ===== instruction parsers (tokens after mnemonic) =================
428
429func parse_rrr(A: *Asm, t: *AsmTok,
             opcode: i64, funct3: i64, funct7: i64) -> i64 {
  let rd: i64 = expect_reg(A, t); if rd < 0 { return -1 }
  if expect_punct(A, t, 0x2C) != 0 { return -1 }
  let rs1: i64 = expect_reg(A, t); if rs1 < 0 { return -1 }
  if expect_punct(A, t, 0x2C) != 0 { return -1 }
  let rs2: i64 = expect_reg(A, t); if rs2 < 0 { return -1 }
  return enc_r(opcode, funct3, funct7, rd, rs1, rs2)
437}
438func parse_rri(A: *Asm, t: *AsmTok, opcode: i64, funct3: i64) -> i64 {
  let rd: i64 = expect_reg(A, t); if rd < 0 { return -1 }
  if expect_punct(A, t, 0x2C) != 0 { return -1 }
  let rs1: i64 = expect_reg(A, t); if rs1 < 0 { return -1 }
  if expect_punct(A, t, 0x2C) != 0 { return -1 }
  var err: i64 = 0
  let imm: i64 = expect_int(A, t, &err)
  if err != 0 { return -1 }
  return enc_i(opcode, funct3, rd, rs1, imm)
447}
448func parse_mem(A: *Asm, t: *AsmTok, is_store: i64, funct3: i64) -> i64 {
  let first: i64 = expect_reg(A, t); if first < 0 { return -1 }
  if expect_punct(A, t, 0x2C) != 0 { return -1 }
  var err: i64 = 0
  let imm: i64 = expect_int(A, t, &err); if err != 0 { return -1 }
  if expect_punct(A, t, 0x28) != 0 { return -1 }
  let second: i64 = expect_reg(A, t); if second < 0 { return -1 }
  if expect_punct(A, t, 0x29) != 0 { return -1 }
  if is_store { return enc_s(0x23, funct3, second, first, imm) }
  return enc_i(0x03, funct3, first, second, imm)
458}
459// `li rd, imm` -- macro that expands to 1, 2, or 6 instructions
460// depending on the immediate width.  The old form silently truncated
461// to 12 bits via enc_i's masking, mangling 64-bit literals like
462// 0x0001000100010001 (the SIMD smoke's packed-i16 pattern) into
463// a stored value of 1.  Fixed 2026-05-16 after the silent-truncate
464// bug took 2 hours to bisect through the self-host SIMD pipeline.
465//
466// Expansion forms:
467//   12-bit signed   : addi rd, zero, imm
468//   32-bit signed   : lui rd, hi20 ; addi rd, rd, lo12 (sign-adjusted)
469//   64-bit any      : lui rd, h32_hi20 ; addi rd, rd, h32_lo12
470//                     slli rd, rd, 32
471//                     lui t6, l32_hi20 ; addi t6, t6, l32_lo12
472//                     add rd, rd, t6
473//
474// The 64-bit form uses t6 (= x31) as scratch -- matches the
475// codegen-side scratch reservation used by nx_riscv.nx's
476// emit_sp_* helpers.
477func parse_li(A: *Asm, t: *AsmTok) -> i64 {
  let rd: i64 = expect_reg(A, t); if rd < 0 { return -1 }
  if expect_punct(A, t, 0x2C) != 0 { return -1 }
  var err: i64 = 0
  let imm: i64 = expect_int(A, t, &err); if err != 0 { return -1 }
  // 12-bit signed fits in one addi.
  if imm >= -2048 {
      if imm <= 2047 {
          return enc_i(0x13, 0, rd, 0, imm)
      }
  }
  // Does the immediate fit in signed 32-bit?  If so, use the
  // 2-instruction lui+addi form.  Otherwise fall through to the
  // 8-instruction 64-bit construction.
  var fits: i64 = 0
  if imm >= (0 - 2147483648) {
      if imm <= 2147483647 {
          fits = 1
      }
  }
  if fits == 1 {
      let hi20: i64 = (imm + 0x800) >> 12
      let lo12: i64 = imm - (hi20 << 12)
      let lui_word: i64 = enc_u(0x37, rd, hi20)
      emit_u32(A, lui_word)
      if lo12 == 0 {
          // Returning nop would still emit a u32; we want NO further
          // instruction.  Hack: return enc that the dispatcher emits,
          // then deduct... Simpler: emit one safe addi rd, rd, 0
          // which is `mv rd, rd` (no-op).  Cheaper alternative:
          // return the second emit ourselves and let dispatch emit
          // a nop.  Use the dispatcher's slot for the addi.
          return enc_i(0x13, 0, rd, rd, 0)
      }
      return enc_i(0x13, 0, rd, rd, lo12)
  }
  // 64-bit case.  Build via high32 << 32 | low32.
  let hi32: i64 = (imm >> 32) & 0xFFFFFFFF
  let lo32: i64 = imm & 0xFFFFFFFF
  // Hi32 -- split into hi20 + lo12.  Treat as signed 32-bit when
  // computing the addi adjustment.
  var hi32_s: i64 = hi32
  if hi32_s >= 0x80000000 { hi32_s = hi32_s - 0x100000000 }
  let hh20: i64 = (hi32_s + 0x800) >> 12
  let hl12: i64 = hi32_s - (hh20 << 12)
  // Lo32 -- same split.  We need t6 to hold a value WHOSE low 32
  // bits = lo32 and whose upper bits ZERO -- otherwise the `add`
  // at the end would over-extend into the upper half.  The
  // canonical trick: shift up then down to zero-extend.  Easier:
  // use `srli` to clear upper bits before add.
  var lo32_s: i64 = lo32
  if lo32_s >= 0x80000000 { lo32_s = lo32_s - 0x100000000 }
  let lh20: i64 = (lo32_s + 0x800) >> 12
  let ll12: i64 = lo32_s - (lh20 << 12)
  // Sequence:
  //   lui rd, hh20
  //   addi rd, rd, hl12
  //   slli rd, rd, 32
  //   lui t6, lh20
  //   addi t6, t6, ll12
  //   slli t6, t6, 32 ; srli t6, t6, 32   (zero-extend)
  //   add rd, rd, t6
  emit_u32(A, enc_u(0x37, rd, hh20))
  emit_u32(A, enc_i(0x13, 0, rd, rd, hl12))
  emit_u32(A, enc_i(0x13, 1, rd, rd, 32))           // slli rd, rd, 32
  emit_u32(A, enc_u(0x37, 31, lh20))                // lui t6, lh20
  emit_u32(A, enc_i(0x13, 0, 31, 31, ll12))         // addi t6, t6, ll12
  emit_u32(A, enc_i(0x13, 1, 31, 31, 32))           // slli t6, t6, 32
  emit_u32(A, enc_i(0x13, 5, 31, 31, 32))           // srli t6, t6, 32 (zero-ext low32)
  return enc_r(0x33, 0, 0, rd, rd, 31)              // add rd, rd, t6
547}
548func parse_mv(A: *Asm, t: *AsmTok) -> i64 {
  let rd: i64 = expect_reg(A, t); if rd < 0 { return -1 }
  if expect_punct(A, t, 0x2C) != 0 { return -1 }
  let rs: i64 = expect_reg(A, t); if rs < 0 { return -1 }
  return enc_i(0x13, 0, rd, rs, 0)
553}
554// `srai rd, rs1, shamt` -- arithmetic right shift (sign-extending).
555// Distinct from srli (logical right shift, zero-fill) by funct7
556// bits 31:26 = 010000 (= 0x10 in the high 6 bits of the immediate
557// field, which becomes shamt's neighbor in the I-type encoding).
558// nxasm previously routed srai through the same parse_rri as srli,
559// silently turning `srai t6, t6, 48` into a logical shift -- which
560// is what made vreduce_min/max return UNSIGNED i16 values instead
561// of sign-extended i64 (2026-05-16, bisected from
562// _self_host_pack4_neg_test.nx returning 65537 instead of 1).
563func parse_srai(A: *Asm, t: *AsmTok) -> i64 {
  let rd: i64 = expect_reg(A, t); if rd < 0 { return -1 }
  if expect_punct(A, t, 0x2C) != 0 { return -1 }
  let rs1: i64 = expect_reg(A, t); if rs1 < 0 { return -1 }
  if expect_punct(A, t, 0x2C) != 0 { return -1 }
  var err: i64 = 0
  let shamt: i64 = expect_int(A, t, &err)
  if err != 0 { return -1 }
  // Encoding: bits 31:26 = 010000 (funct6 for srai in RV64), bits
  // 25:20 = shamt (6 bits since XLEN=64).  Combined imm field
  // (bits 31:20) = 0x400 | (shamt & 0x3F).
  let imm: i64 = 0x400 | (shamt & 0x3F)
  return enc_i(0x13, 5, rd, rs1, imm)
576}
577
578// `j label` and `jal label` -- we parse just the label identifier,
579// look up its address, compute offset from cur_addr (pass 2 only),
580// and encode a JAL instruction.  rd=0 for `j`, rd=1 for `jal` unless
581// a rd is given explicitly.
582func parse_j_label(A: *Asm, t: *AsmTok, rd: i64) -> i64 {
  next_tok(A, t)
  if t.kind != 1 {
      sys_write(2, "nxasm:j: kind != 1\n" as *u8, 19)
      return -1
  }
  if A.pass == 1 {
      return enc_j(0x6F, rd, 0)     // pass 1: offset unknown, any value
  }
  let idx: i64 = label_find(A, t.start, t.len)
  if idx < 0 {
      sys_write(2, "nxasm:j: label not found '" as *u8, 26)
      var di: i64 = 0
      while di < t.len {
          sys_write(2, (((A.src as i64) + t.start + di) as *u8), 1)
          di = di + 1
      }
      sys_write(2, "' n_labels=" as *u8, 11)
      let dnbuf: *u8 = sys_mmap(16)
      var dn: i64 = A.n_labels
      var dk: i64 = 0
      if dn == 0 { dnbuf[dk] = 0x30; dk = 1 }
      while dn > 0 {
          dnbuf[dk] = 0x30 + (dn - (dn / 10) * 10)
          dn = dn / 10
          dk = dk + 1
      }
      var dj: i64 = dk - 1
      while dj >= 0 {
          sys_write(2, (((dnbuf as i64) + dj) as *u8), 1)
          dj = dj - 1
      }
      sys_write(2, "\n" as *u8, 1)
      return -1
  }
  let base: i64 = A.labels as i64
  let lab: *Label = (base + idx * 32) as *Label
  let off: i64 = lab.addr - A.cur_addr
  return enc_j(0x6F, rd, off)
621}
622
623// `bnez rs1, label` -> beq rs1, zero, label with funct3=1 (bne).
624// `beqz rs1, label` -> beq rs1, zero, label with funct3=0 (beq).
625func parse_branch_zero(A: *Asm, t: *AsmTok, funct3: i64) -> i64 {
  let rs1: i64 = expect_reg(A, t); if rs1 < 0 { return -1 }
  if expect_punct(A, t, 0x2C) != 0 { return -1 }
  next_tok(A, t)
  if t.kind != 1 { return -1 }
  if A.pass == 1 {
      return enc_b(0x63, funct3, rs1, 0, 0)
  }
  let idx: i64 = label_find(A, t.start, t.len)
  if idx < 0 { return -1 }
  let base: i64 = A.labels as i64
  let lab: *Label = (base + idx * 32) as *Label
  let off: i64 = lab.addr - A.cur_addr
  return enc_b(0x63, funct3, rs1, 0, off)
639}
640
641func parse_ret(A: *Asm, t: *AsmTok) -> i64 { return enc_i(0x67, 0, 0, 1, 0) }
642func parse_ecall(A: *Asm, t: *AsmTok) -> i64 { return enc_i(0x73, 0, 0, 0, 0) }
643
644// B-type branch family (Task #36).  Full 3-operand form:
645//   beq/bne/blt/bge/bltu/bgeu rs1, rs2, label
646// funct3 selects op: 0=BEQ, 1=BNE, 4=BLT, 5=BGE, 6=BLTU, 7=BGEU.
647// Pass 1: emit a placeholder (offset=0) so label_define sees the size.
648// Pass 2: resolve label address and emit the real offset.
649func parse_branch(A: *Asm, t: *AsmTok, funct3: i64) -> i64 {
  let rs1: i64 = expect_reg(A, t); if rs1 < 0 { return -1 }
  if expect_punct(A, t, 0x2C) != 0 { return -1 }
  let rs2: i64 = expect_reg(A, t); if rs2 < 0 { return -1 }
  if expect_punct(A, t, 0x2C) != 0 { return -1 }
  next_tok(A, t)
  if t.kind != 1 { return -1 }
  if A.pass == 1 {
      return enc_b(0x63, funct3, rs1, rs2, 0)
  }
  let idx: i64 = label_find(A, t.start, t.len)
  if idx < 0 { return -1 }
  let base: i64 = A.labels as i64
  let lab: *Label = (base + idx * 32) as *Label
  let off: i64 = lab.addr - A.cur_addr
  return enc_b(0x63, funct3, rs1, rs2, off)
665}
666
667// ===== CSR instructions (Task #35) ================================
668//
669// CSR ops are I-type with opcode=0x73, funct3 selecting the op:
670//   001 CSRRW   010 CSRRS   011 CSRRC
671//   101 CSRRWI  110 CSRRSI  111 CSRRCI
672// Immediate field carries the 12-bit CSR address.
673//
674// Full form: `csrrw rd, csr, rs` -- 3 operands.
675// Pseudo:    `csrr  rd, csr`     = csrrs rd, csr, x0  (read)
676//            `csrw  csr, rs`     = csrrw x0, csr, rs  (write)
677//            `csrs  csr, rs`     = csrrs x0, csr, rs  (set bits)
678//            `csrc  csr, rs`     = csrrc x0, csr, rs  (clear bits)
679//
680// CSR address may be a numeric literal (nxc2 emits 2816, 832 etc.) OR
681// a symbolic name (kernel .S files use mstatus, mhartid, etc.).
682
683// Read CSR address from next token: accepts either integer literal
684// or known symbolic name (mstatus / mhartid / mscratch / mepc /
685// mtvec / mcause / mtval / mie / mip / mcycle).  Returns the 12-bit
686// CSR address; sets *err on unknown name or non-int/non-ident token.
687func expect_csr_or_int(A: *Asm, t: *AsmTok, err: *i64) -> i64 {
  next_tok(A, t)
  *err = 0
  if t.kind == 2 { return t.val }
  if t.kind == 1 {
      let off: i64 = t.start
      let n:   i64 = t.len
      if n == 3 {
          if s_eq3(A.src, off, n, 0x6D, 0x69, 0x65) { return 0x304 }  // mie
          if s_eq3(A.src, off, n, 0x6D, 0x69, 0x70) { return 0x344 }  // mip
      }
      if n == 4 {
          if s_eq4(A.src, off, n, 0x6D, 0x65, 0x70, 0x63) { return 0x341 }  // mepc
      }
      if n == 5 {
          if s_eq5(A.src, off, n, 0x6D, 0x74, 0x76, 0x65, 0x63) { return 0x305 }  // mtvec
          if s_eq5(A.src, off, n, 0x6D, 0x74, 0x76, 0x61, 0x6C) { return 0x343 }  // mtval
      }
      if n == 6 {
          // mcause / mcycle (both length-6, common prefix "mc")
          let mcause_pat: *u8 = "mcause" as *u8
          if s_eq6(A.src, off, n, mcause_pat, 6) { return 0x342 }
          let mcycle_pat: *u8 = "mcycle" as *u8
          if s_eq6(A.src, off, n, mcycle_pat, 6) { return 0xB00 }
      }
      if n == 7 {
          let mstatus_pat: *u8 = "mstatus" as *u8
          if s_eq6(A.src, off, n, mstatus_pat, 7) { return 0x300 }
          let mhartid_pat: *u8 = "mhartid" as *u8
          if s_eq6(A.src, off, n, mhartid_pat, 7) { return 0xF14 }
      }
      if n == 8 {
          let mscratch_pat: *u8 = "mscratch" as *u8
          if s_eq6(A.src, off, n, mscratch_pat, 8) { return 0x340 }
      }
  }
  *err = 1
  return 0
725}
726
727// `csrrw rd, csr, rs` (3-operand form, used by csrrw/csrrs/csrrc).
728func parse_csr_full(A: *Asm, t: *AsmTok, funct3: i64) -> i64 {
  let rd: i64 = expect_reg(A, t); if rd < 0 { return -1 }
  if expect_punct(A, t, 0x2C) != 0 { return -1 }
  var err: i64 = 0
  let csr: i64 = expect_csr_or_int(A, t, &err); if err != 0 { return -1 }
  if expect_punct(A, t, 0x2C) != 0 { return -1 }
  let rs: i64 = expect_reg(A, t); if rs < 0 { return -1 }
  return enc_i(0x73, funct3, rd, rs, csr & 0xFFF)
736}
737
738// `csrr rd, csr` = csrrs rd, csr, x0.
739func parse_csrr(A: *Asm, t: *AsmTok) -> i64 {
  let rd: i64 = expect_reg(A, t); if rd < 0 { return -1 }
  if expect_punct(A, t, 0x2C) != 0 { return -1 }
  var err: i64 = 0
  let csr: i64 = expect_csr_or_int(A, t, &err); if err != 0 { return -1 }
  return enc_i(0x73, 2, rd, 0, csr & 0xFFF)
745}
746
747// `csrw csr, rs` = csrrw x0, csr, rs.  Also covers csrs / csrc with
748// different funct3.
749func parse_csr_write(A: *Asm, t: *AsmTok, funct3: i64) -> i64 {
  var err: i64 = 0
  let csr: i64 = expect_csr_or_int(A, t, &err); if err != 0 { return -1 }
  if expect_punct(A, t, 0x2C) != 0 { return -1 }
  let rs: i64 = expect_reg(A, t); if rs < 0 { return -1 }
  return enc_i(0x73, funct3, 0, rs, csr & 0xFFF)
755}
756
757// seqz rd, rs -- rd = (rs == 0)?  Pseudo: sltiu rd, rs, 1.
758func parse_seqz(A: *Asm, t: *AsmTok) -> i64 {
  let rd: i64 = expect_reg(A, t); if rd < 0 { return -1 }
  if expect_punct(A, t, 0x2C) != 0 { return -1 }
  let rs: i64 = expect_reg(A, t); if rs < 0 { return -1 }
  return enc_i(0x13, 3, rd, rs, 1)      // sltiu rd, rs, 1
763}
764
765// snez rd, rs -- rd = (rs != 0)?  Pseudo: sltu rd, x0, rs.
766func parse_snez(A: *Asm, t: *AsmTok) -> i64 {
  let rd: i64 = expect_reg(A, t); if rd < 0 { return -1 }
  if expect_punct(A, t, 0x2C) != 0 { return -1 }
  let rs: i64 = expect_reg(A, t); if rs < 0 { return -1 }
  return enc_r(0x33, 3, 0, rd, 0, rs)   // sltu rd, x0, rs
771}
772
773// `la rd, sym` -- two-instruction expansion:
774//   auipc rd, (sym_hi20)
775//   addi  rd, rd, (sym_lo12)
776// emit_u32 the first word inside, return the second so the caller
777// emits it normally.  pass-1: advance cur_addr by 8.
778func parse_la(A: *Asm, t: *AsmTok) -> i64 {
  let rd: i64 = expect_reg(A, t); if rd < 0 { return -1 }
  if expect_punct(A, t, 0x2C) != 0 { return -1 }
  next_tok(A, t)
  if t.kind != 1 { return -1 }
  var tgt: i64 = 0
  if A.pass == 2 {
      let idx: i64 = label_find(A, t.start, t.len)
      if idx < 0 {
          // Task #39 diagnostic: name the missing label so the
          // dispatcher's "bad mnemonic" message points the user at
          // the actual problem (label resolution, not parsing).
          sys_write(2, "nxasm:la label-not-found '" as *u8, 26)
          var di: i64 = 0
          while di < t.len {
              sys_write(2, (((A.src as i64) + t.start + di) as *u8), 1)
              di = di + 1
          }
          sys_write(2, "'\n" as *u8, 2)
          return -1
      }
      let base: i64 = A.labels as i64
      let lab: *Label = (base + idx * 32) as *Label
      tgt = lab.addr - A.cur_addr
  }
  // Split into hi20 + lo12 with proper sign handling: lo12 is
  // sign-extended by the addi, so pre-add 0x800 to tgt before
  // taking the hi20 if the low 12 bits are negative-signed.
  var hi: i64 = (tgt + 0x800) >> 12
  let lo: i64 = tgt - (hi << 12)
  let auipc_word: i64 = enc_u(0x17, rd, hi)
  emit_u32(A, auipc_word)
  // Return the addi; caller emits it.
  return enc_i(0x13, 0, rd, rd, lo)
812}
813
814// `tail sym` -- tail call: auipc x6, hi; jalr x0, lo(x6).
815// We follow RISC-V ABI: t1 (x6) is the staging register.
816func parse_tail(A: *Asm, t: *AsmTok) -> i64 {
  next_tok(A, t)
  if t.kind != 1 { return -1 }
  var tgt: i64 = 0
  if A.pass == 2 {
      let idx: i64 = label_find(A, t.start, t.len)
      if idx < 0 { return -1 }
      let base: i64 = A.labels as i64
      let lab: *Label = (base + idx * 32) as *Label
      tgt = lab.addr - A.cur_addr
  }
  var hi: i64 = (tgt + 0x800) >> 12
  let lo: i64 = tgt - (hi << 12)
  let auipc_word: i64 = enc_u(0x17, 6, hi)     // auipc t1, hi
  emit_u32(A, auipc_word)
  return enc_i(0x67, 0, 0, 6, lo)              // jalr x0, t1, lo
832}
833
834// ===== directive handlers ==========================================
835//
836// Only those nxc2 emits; others fall through to a no-op dispatcher.
837
838// `.byte N [, N ...]`
839func handle_byte(A: *Asm, t: *AsmTok) -> i64 {
  var more: i64 = 1
  while more {
      var err: i64 = 0
      let v: i64 = expect_int(A, t, &err)
      if err != 0 { return -1 }
      emit_byte(A, v)
      // Peek next token; if it's a comma, consume and continue.
      let save: i64 = A.pos
      next_tok(A, t)
      if t.kind == 3 {
          if t.val == 0x2C {
              // comma -- keep going
              more = 1
          }
          if t.val != 0x2C {
              A.pos = save
              more = 0
          }
      }
      if t.kind != 3 {
          A.pos = save
          more = 0
      }
  }
  return 0
865}
866
867// `.asciz "..."` -- emit the string bytes + a trailing NUL, with
868// gas-style escape processing: \n -> 0x0A, \t -> 0x09, \r -> 0x0D,
869// \\ -> 0x5C, \" -> 0x22, \0 -> 0x00, \ooo -> octal byte.  Without
870// this, a `.asciz "hi\n"` emitted by nxc.nx's globals dump would
871// land as 4 literal bytes h, i, \, n -- and sys_write(1, p, 3) would
872// print "hi\\".  Closes nxasm side of T#selfhost-003.
873// `.skip N` / `.zero N` -- emit N zero bytes.  Used for BSS-style
874// reservations (trap.S allocates 8 KiB trap stack; nxc2-emitted .s
875// uses .zero N for static array reservations).  Without this nxasm
876// silently skipped these directives and labels following them landed
877// at the WRONG cur_addr.  Closes Phase F1 structural blocker class
878// for single-segment kernel builds.
879func handle_skip(A: *Asm, t: *AsmTok) -> i64 {
  var err: i64 = 0
  let n: i64 = expect_int(A, t, &err)
  if err != 0 { return -1 }
  if n <= 0 { return 0 }
  var i: i64 = 0
  while i < n {
      emit_byte(A, 0)
      i = i + 1
  }
  return 0
890}
891
892func handle_asciz(A: *Asm, t: *AsmTok) -> i64 {
  next_tok(A, t)
  if t.kind != 4 { return -1 }
  // Walk t.start+1 .. t.start+t.len-1 (skip surrounding quotes).
  var i: i64 = 1
  let end: i64 = t.len - 1
  while i < end {
      let c: i64 = A.src[t.start + i]
      if c == 0x5C {
          if i + 1 < end {
              let nx: i64 = A.src[t.start + i + 1]
              if nx == 0x6E { emit_byte(A, 0x0A); i = i + 2; continue }  // \n
              if nx == 0x74 { emit_byte(A, 0x09); i = i + 2; continue }  // \t
              if nx == 0x72 { emit_byte(A, 0x0D); i = i + 2; continue }  // \r
              if nx == 0x5C { emit_byte(A, 0x5C); i = i + 2; continue }  // \\
              if nx == 0x22 { emit_byte(A, 0x22); i = i + 2; continue }  // \"
              if nx == 0x30 {
                  // \0 (single char, NOT followed by more octal digits)
                  // OR \ooo (three octal digits).  Distinguish by
                  // looking at the next two characters.
                  if i + 3 < end {
                      let o2: i64 = A.src[t.start + i + 2]
                      let o3: i64 = A.src[t.start + i + 3]
                      if o2 >= 0x30 {
                          if o2 <= 0x37 {
                              if o3 >= 0x30 {
                                  if o3 <= 0x37 {
                                      let b: i64 = ((nx - 0x30) << 6) |
                                                   ((o2 - 0x30) << 3) |
                                                   (o3 - 0x30)
                                      emit_byte(A, b)
                                      i = i + 4
                                      continue
                                  }
                              }
                          }
                      }
                  }
                  emit_byte(A, 0x00); i = i + 2; continue
              }
              // \ooo for 1..3 -- treat first digit as octal escape.
              if nx >= 0x31 {
                  if nx <= 0x37 {
                      if i + 3 < end {
                          let o2: i64 = A.src[t.start + i + 2]
                          let o3: i64 = A.src[t.start + i + 3]
                          if o2 >= 0x30 {
                              if o2 <= 0x37 {
                                  if o3 >= 0x30 {
                                      if o3 <= 0x37 {
                                          let b: i64 = ((nx - 0x30) << 6) |
                                                       ((o2 - 0x30) << 3) |
                                                       (o3 - 0x30)
                                          emit_byte(A, b)
                                          i = i + 4
                                          continue
                                      }
                                  }
                              }
                          }
                      }
                  }
              }
              // Unknown escape: pass through both bytes (gas warns;
              // we keep the backslash + literal char).
              emit_byte(A, c)
              emit_byte(A, nx)
              i = i + 2
              continue
          }
      }
      emit_byte(A, c)
      i = i + 1
  }
  emit_byte(A, 0)
  return 0
968}
969
970// `.word N` -- emit one 32-bit little-endian word.  Used by
971// rv_emit_simd_vdot_i16 (and future SIMD/SIMT lowerings) to emit
972// pre-encoded RVV instructions without needing a full vector
973// mnemonic parser in nxasm.  Bits-up sovereign path: nx_riscv.nx
974// pre-computes the 32-bit RVV encoding (substituting in the
975// run-time register IDs) and hands the assembler an opaque word.
976//
977// Supports multiple comma-separated words on one line, matching the
978// `.byte` shape, so the codegen can pack a whole RVV chain into a
979// single directive if desired.
980func handle_word(A: *Asm, t: *AsmTok) -> i64 {
  var more: i64 = 1
  while more {
      var err: i64 = 0
      let v: i64 = expect_int(A, t, &err)
      if err != 0 { return -1 }
      emit_u32(A, v)
      let save: i64 = A.pos
      next_tok(A, t)
      if t.kind == 3 {
          if t.val == 0x2C { more = 1 }
          if t.val != 0x2C { A.pos = save; more = 0 }
      }
      if t.kind != 3 { A.pos = save; more = 0 }
  }
  return 0
996}
997
998// Ignored directive: eat the rest of the line (everything till \n).
999// Detects via tokens already having different lines; simpler: eat
1000// tokens until we hit a token whose start column is after a newline
1001// in source.  Crudest but works: consume tokens while the next char
1002// in src is NOT a newline.
1003func skip_to_newline(A: *Asm) -> i64 {
  while A.pos < A.src_len {
      let c: i64 = A.src[A.pos]
      if c == 0x0A { return 0 }
      A.pos = A.pos + 1
  }
  return 0
1010}
1011
1012// ===== mnemonic dispatch ============================================
1013
1014func assemble_mnemonic(A: *Asm, t: *AsmTok, off: i64, n: i64) -> i64 {
  // 1-char mnemonics: "j label"
  if n == 1 {
      if A.src[off] == 0x6A { return parse_j_label(A, t, 0) }
  }
  if n == 2 {
      if s_eq2(A.src, off, n, 0x6C, 0x69) { return parse_li(A, t) }        // li
      if s_eq2(A.src, off, n, 0x6D, 0x76) { return parse_mv(A, t) }        // mv
      if s_eq2(A.src, off, n, 0x6C, 0x64) { return parse_mem(A, t, 0, 3) } // ld
      if s_eq2(A.src, off, n, 0x73, 0x64) { return parse_mem(A, t, 1, 3) } // sd
      if s_eq2(A.src, off, n, 0x73, 0x62) { return parse_mem(A, t, 1, 0) } // sb (store byte)
      if s_eq2(A.src, off, n, 0x73, 0x68) { return parse_mem(A, t, 1, 1) } // sh (store halfword)
      if s_eq2(A.src, off, n, 0x73, 0x77) { return parse_mem(A, t, 1, 2) } // sw (store word)
      if s_eq2(A.src, off, n, 0x6C, 0x61) { return parse_la(A, t)  }        // la
      if s_eq2(A.src, off, n, 0x6F, 0x72) { return parse_rrr(A, t, 0x33, 6, 0) }  // or
  }
  if n == 3 {
      if s_eq3(A.src, off, n, 0x72, 0x65, 0x74) { return parse_ret(A, t) }
      if s_eq3(A.src, off, n, 0x61, 0x64, 0x64) { return parse_rrr(A, t, 0x33, 0, 0) }       // add
      if s_eq3(A.src, off, n, 0x73, 0x75, 0x62) { return parse_rrr(A, t, 0x33, 0, 0x20) }    // sub
      if s_eq3(A.src, off, n, 0x6A, 0x61, 0x6C) { return parse_j_label(A, t, 1) }             // jal
      if s_eq3(A.src, off, n, 0x61, 0x6E, 0x64) { return parse_rrr(A, t, 0x33, 7, 0) }       // and
      if s_eq3(A.src, off, n, 0x78, 0x6F, 0x72) { return parse_rrr(A, t, 0x33, 4, 0) }       // xor
      if s_eq3(A.src, off, n, 0x6D, 0x75, 0x6C) { return parse_rrr(A, t, 0x33, 0, 1) }       // mul (M-ext)
      if s_eq3(A.src, off, n, 0x64, 0x69, 0x76) { return parse_rrr(A, t, 0x33, 4, 1) }       // div
      if s_eq3(A.src, off, n, 0x72, 0x65, 0x6D) { return parse_rrr(A, t, 0x33, 6, 1) }       // rem
      if s_eq3(A.src, off, n, 0x73, 0x6C, 0x6C) { return parse_rrr(A, t, 0x33, 1, 0) }       // sll
      if s_eq3(A.src, off, n, 0x73, 0x72, 0x6C) { return parse_rrr(A, t, 0x33, 5, 0) }       // srl
      if s_eq3(A.src, off, n, 0x73, 0x72, 0x61) { return parse_rrr(A, t, 0x33, 5, 0x20) }    // sra
      if s_eq3(A.src, off, n, 0x73, 0x6C, 0x74) { return parse_rrr(A, t, 0x33, 2, 0) }       // slt
      if s_eq3(A.src, off, n, 0x6C, 0x77, 0x75) { return parse_mem(A, t, 0, 6) }             // lwu
      if s_eq3(A.src, off, n, 0x6E, 0x6F, 0x70) { return enc_i(0x13, 0, 0, 0, 0) }           // nop
      // B-type branches (Task #36).  funct3: 0=beq, 1=bne, 4=blt, 5=bge.
      if s_eq3(A.src, off, n, 0x62, 0x65, 0x71) { return parse_branch(A, t, 0) }              // beq
      if s_eq3(A.src, off, n, 0x62, 0x6E, 0x65) { return parse_branch(A, t, 1) }              // bne
      if s_eq3(A.src, off, n, 0x62, 0x6C, 0x74) { return parse_branch(A, t, 4) }              // blt
      if s_eq3(A.src, off, n, 0x62, 0x67, 0x65) { return parse_branch(A, t, 5) }              // bge
  }
  if n == 4 {
      if s_eq4(A.src, off, n, 0x61, 0x64, 0x64, 0x69) { return parse_rri(A, t, 0x13, 0) }   // addi
      if s_eq4(A.src, off, n, 0x62, 0x6E, 0x65, 0x7A) { return parse_branch_zero(A, t, 1) } // bnez
      if s_eq4(A.src, off, n, 0x62, 0x65, 0x71, 0x7A) { return parse_branch_zero(A, t, 0) } // beqz
      if s_eq4(A.src, off, n, 0x6A, 0x61, 0x6C, 0x72) { return parse_rri(A, t, 0x67, 0) }   // jalr
      if s_eq4(A.src, off, n, 0x63, 0x61, 0x6C, 0x6C) { return parse_j_label(A, t, 1) }     // call
      if s_eq4(A.src, off, n, 0x74, 0x61, 0x69, 0x6C) { return parse_tail(A, t) }            // tail
      if s_eq4(A.src, off, n, 0x73, 0x65, 0x71, 0x7A) { return parse_seqz(A, t) }            // seqz
      if s_eq4(A.src, off, n, 0x73, 0x6E, 0x65, 0x7A) { return parse_snez(A, t) }            // snez
      if s_eq4(A.src, off, n, 0x78, 0x6F, 0x72, 0x69) { return parse_rri(A, t, 0x13, 4) }   // xori
      if s_eq4(A.src, off, n, 0x61, 0x6E, 0x64, 0x69) { return parse_rri(A, t, 0x13, 7) }   // andi
      if s_eq4(A.src, off, n, 0x73, 0x6C, 0x6C, 0x69) { return parse_rri(A, t, 0x13, 1) }   // slli
      if s_eq4(A.src, off, n, 0x73, 0x72, 0x6C, 0x69) { return parse_rri(A, t, 0x13, 5) }   // srli
      if s_eq4(A.src, off, n, 0x73, 0x72, 0x61, 0x69) { return parse_srai(A, t) }            // srai -- funct6=0x10
      if s_eq4(A.src, off, n, 0x6C, 0x62, 0x75, 0x20) { return parse_mem(A, t, 0, 4) }       // lbu (trailing space)
      // CSR pseudo-ops (Task #35).  csr*=0x63 0x73 0x72 prefix.
      if s_eq4(A.src, off, n, 0x63, 0x73, 0x72, 0x72) { return parse_csrr(A, t) }            // csrr  rd, csr
      if s_eq4(A.src, off, n, 0x63, 0x73, 0x72, 0x77) { return parse_csr_write(A, t, 1) }    // csrw  csr, rs
      if s_eq4(A.src, off, n, 0x63, 0x73, 0x72, 0x73) { return parse_csr_write(A, t, 2) }    // csrs  csr, rs
      if s_eq4(A.src, off, n, 0x63, 0x73, 0x72, 0x63) { return parse_csr_write(A, t, 3) }    // csrc  csr, rs
      // B-type 4-letter mnemonics (Task #36).  bltu=6, bgeu=7.
      if s_eq4(A.src, off, n, 0x62, 0x6C, 0x74, 0x75) { return parse_branch(A, t, 6) }       // bltu
      if s_eq4(A.src, off, n, 0x62, 0x67, 0x65, 0x75) { return parse_branch(A, t, 7) }       // bgeu
  }
  if n == 3 {
      // Fall-back 3-char mnemonics that start with 'l': lb, lh, lw, sh, sw
      // (duplicate table so length-3 loads land here after early matches).
  }
  if n == 5 {
      if s_eq5(A.src, off, n, 0x65, 0x63, 0x61, 0x6C, 0x6C) { return parse_ecall(A, t) }    // ecall
      // CSR full forms (3-operand: rd, csr, rs).
      if s_eq5(A.src, off, n, 0x63, 0x73, 0x72, 0x72, 0x77) { return parse_csr_full(A, t, 1) } // csrrw
      if s_eq5(A.src, off, n, 0x63, 0x73, 0x72, 0x72, 0x73) { return parse_csr_full(A, t, 2) } // csrrs
      if s_eq5(A.src, off, n, 0x63, 0x73, 0x72, 0x72, 0x63) { return parse_csr_full(A, t, 3) } // csrrc
  }
  // System instructions (no operands): wfi, mret, sret, ebreak.
  if n == 3 {
      if s_eq3(A.src, off, n, 0x77, 0x66, 0x69) { return enc_i(0x73, 0, 0, 0, 0x105) }       // wfi
  }
  if n == 4 {
      if s_eq4(A.src, off, n, 0x6D, 0x72, 0x65, 0x74) { return enc_i(0x73, 0, 0, 0, 0x302) } // mret
      if s_eq4(A.src, off, n, 0x73, 0x72, 0x65, 0x74) { return enc_i(0x73, 0, 0, 0, 0x102) } // sret
  }
  if n == 6 {
      let ebreak_pat: *u8 = "ebreak" as *u8
      if s_eq6(A.src, off, n, ebreak_pat, 6) { return enc_i(0x73, 0, 0, 0, 1) }              // ebreak
  }
  // Short load/store dispatch (length 2-3, final byte 'b'/'h'/'w'/'u').
  if n == 2 {
      if A.src[off] == 0x6C {
          if A.src[off+1] == 0x62 { return parse_mem(A, t, 0, 0) }    // lb
          if A.src[off+1] == 0x68 { return parse_mem(A, t, 0, 1) }    // lh
          if A.src[off+1] == 0x77 { return parse_mem(A, t, 0, 2) }    // lw
      }
  }
  if n == 3 {
      if s_eq3(A.src, off, n, 0x6C, 0x62, 0x75) { return parse_mem(A, t, 0, 4) }  // lbu
      if s_eq3(A.src, off, n, 0x6C, 0x68, 0x75) { return parse_mem(A, t, 0, 5) }  // lhu
  }
  return -1
1112}
1113
1114// ===== main assembly loop ===========================================
1115//
1116// Walk tokens line-by-line.  Each line is either:
1117//   * IDENT ":"                  -> label definition
1118//   * IDENT starting with "."    -> directive
1119//   * IDENT otherwise            -> mnemonic
1120// After handling, we skip rest-of-line (any remaining tokens) and
1121// move to next line.
1122
1123// Forward-decl: alloc is defined after assemble_pass.
1124func alloc(size: i64) -> *u8;
1125
1126func assemble_pass(A: *Asm, t: *AsmTok) -> i64 {
  A.pos = 0
  A.cur_addr = 0
  A.out_pos = 0
  var err: i64 = 0
  while err == 0 {
      next_tok(A, t)
      if t.kind == 0 { return 0 }
      if t.kind != 1 {
          // Unexpected leading token -- skip to newline and retry.
          skip_to_newline(A)
          continue
      }
      let off: i64 = t.start
      let n: i64 = t.len
1141
      // Label?  Scan forward in src (NOT via lex_one, whose
      // token-struct pointer-write path has proved fragile).
      // Skip whitespace/newlines from A.pos; if the next non-ws
      // char is ':', we have a label.  We then advance past the
      // ':' too.
      var is_label: i64 = 0
      var scan: i64 = A.pos
      while scan < A.src_len {
          let sc: i64 = A.src[scan]
          if sc == 0x20 { scan = scan + 1; continue }
          if sc == 0x09 { scan = scan + 1; continue }
          if sc == 0x0D { scan = scan + 1; continue }
          if sc == 0x3A {
              is_label = 1
              scan = scan + 1
          }
          // Note: we do NOT skip '\n' -- a ':' on a NEW line is
          // not part of this identifier's label.
          break
      }
      if is_label == 1 {
          if A.pass == 1 {
              label_define(A, off, n)
          }
          A.pos = scan
          continue
      }
1169
      // Directive?  First char is '.' (ASCII 0x2E).
      //
      // Minimal v1 handling: swallow rest of line, regardless of
      // which directive.  .byte / .asciz / etc are not emitted by
      // riscv.nx for the self-host pipeline today; when we need
      // them for string literals later, add per-directive handlers
      // here.  Flag-and-fallthrough avoids the `continue`-inside-
      // nested-if pattern that NishiLang v1 lowers incorrectly.
      var is_directive: i64 = 0
      if A.src[off] == 0x2E {
          is_directive = 1
          // Dispatch the directives we actually emit; ignore others.
          // `.word N[, N...]` -- 32-bit raw word (SIMD/SIMT pre-
          // encoded instructions; lets nx_riscv.nx ship RVV without
          // requiring nxasm to know every vector mnemonic).
          // `.byte N[, N...]` and `.asciz "..."` -- globals dump.
          // Anything else (.text, .globl, .section, .cfi_*, .type,
          // .size, .option) -- skip to newline.
          if n == 5 {
              if s_eq5(A.src, off, n, 0x2E, 0x77, 0x6F, 0x72, 0x64) {
                  handle_word(A, t)
                  continue
              }
              if s_eq5(A.src, off, n, 0x2E, 0x62, 0x79, 0x74, 0x65) {
                  handle_byte(A, t)
                  continue
              }
              if s_eq5(A.src, off, n, 0x2E, 0x73, 0x6B, 0x69, 0x70) {
                  handle_skip(A, t)        // .skip N
                  continue
              }
              if s_eq5(A.src, off, n, 0x2E, 0x7A, 0x65, 0x72, 0x6F) {
                  handle_skip(A, t)        // .zero N (same semantics as .skip)
                  continue
              }
          }
          if n == 6 {
              if s_eq6(A.src, off, n, ".asciz" as *u8, 6) {
                  handle_asciz(A, t)
                  continue
              }
              if s_eq6(A.src, off, n, ".space" as *u8, 6) {
                  handle_skip(A, t)        // .space N (alias of .skip)
                  continue
              }
          }
          skip_to_newline(A)
      }
1218
      if is_directive == 0 {
          // Mnemonic.  Dispatch, emit word, move on.
          let w: i64 = assemble_mnemonic(A, t, off, n)
          if w < 0 {
              // Diagnostic on failure: dump the offending token name +
              // pass + cur_addr so the caller can localize the bug.
              sys_write(2, "nxasm: bad mnemonic '" as *u8, 21)
              var di: i64 = 0
              while di < n {
                  sys_write(2, (((A.src as i64) + off + di) as *u8), 1)
                  di = di + 1
              }
              sys_write(2, "' pass=" as *u8, 7)
              let pbuf: *u8 = sys_mmap(8)
              pbuf[0] = 0x30 + A.pass
              sys_write(2, pbuf, 1)
              sys_write(2, "\n" as *u8, 1)
              err = 1
          }
          if w >= 0 {
              emit_u32(A, w)
          }
      }
  }
  return err
1244}
1245
1246// ===== top-level =====================================================
1247
1248func alloc(size: i64) -> *u8 {
  // Bug fix 2026-05-20: was hardcoded __syscall(222, ...) which is
  // RV64 SYS_MMAP only -- segfaulted on x86_64 (syscall 222 is
  // invalid there).  Now uses SYS_MMAP from nx_syscalls.nx which is
  // @ifdef-switched per arch (x86_64=9, RV64=222).  Closes Task #33
  // x86_64 nxld silent-no-op.
  let raw: i64 = __syscall(SYS_MMAP, 0, size, 3, 0x22, -1, 0)
  return raw as *u8
1256}
1257
1258// One-shot stderr report: where pass-1 stopped + how many labels
1259// it found.  Helps localize early-bail bugs in the tokenize loop
1260// (e.g. a NUL byte in src making next_tok return EOF too early).
1261func nxasm_diag_pass1(A: *Asm, src_len: i64) -> i64 {
  sys_write(2, "nxasm: pass1 stopped at pos=" as *u8, 28)
  let pbuf: *u8 = sys_mmap(32)
  var pn: i64 = A.pos
  var pk: i64 = 0
  if pn == 0 { pbuf[pk] = 0x30; pk = 1 }
  while pn > 0 {
      pbuf[pk] = 0x30 + (pn - (pn / 10) * 10)
      pn = pn / 10
      pk = pk + 1
  }
  var pj: i64 = pk - 1
  while pj >= 0 {
      sys_write(2, (((pbuf as i64) + pj) as *u8), 1)
      pj = pj - 1
  }
  sys_write(2, "/" as *u8, 1)
  let sbuf: *u8 = sys_mmap(32)
  var sn: i64 = src_len
  var sk: i64 = 0
  if sn == 0 { sbuf[sk] = 0x30; sk = 1 }
  while sn > 0 {
      sbuf[sk] = 0x30 + (sn - (sn / 10) * 10)
      sn = sn / 10
      sk = sk + 1
  }
  var sj: i64 = sk - 1
  while sj >= 0 {
      sys_write(2, (((sbuf as i64) + sj) as *u8), 1)
      sj = sj - 1
  }
  sys_write(2, " n_labels=" as *u8, 10)
  let lbuf: *u8 = sys_mmap(32)
  var ln: i64 = A.n_labels
  var lk: i64 = 0
  if ln == 0 { lbuf[lk] = 0x30; lk = 1 }
  while ln > 0 {
      lbuf[lk] = 0x30 + (ln - (ln / 10) * 10)
      ln = ln / 10
      lk = lk + 1
  }
  var lj: i64 = lk - 1
  while lj >= 0 {
      sys_write(2, (((lbuf as i64) + lj) as *u8), 1)
      lj = lj - 1
  }
  sys_write(2, "\n" as *u8, 1)
  return 0
1309}
1310
1311// Assemble `src_len` bytes starting at `src` into `out_buf`, returning
1312// the number of code bytes emitted (out_buf length), or -1 on error.
1313func assemble(src: *u8, src_len: i64, out_buf: *u8, out_cap: i64) -> i64 {
  // 32 bytes per Label * LABELS_CAP slots.  Real-world nxc.s today
  // has ~5K labels; 8K gives 60% headroom.  Bounds-checked in
  // label_define so an overflow now prints + returns -1 instead of
  // writing past the pool.
  let labels_raw: *u8 = alloc(32 * LABELS_CAP)
  let labels: *Label = labels_raw as *Label
1320
  let actx_raw: *u8 = alloc(80)
  let A: *Asm = actx_raw as *Asm
  A.src = src
  A.src_len = src_len
  A.pos = 0
  A.cur_addr = 0
  A.pass = 1
  A.out = out_buf
  A.out_pos = 0
  A.labels = labels
  A.n_labels = 0
1332
  let t_raw: *u8 = alloc(64)
  let t: *AsmTok = t_raw as *AsmTok
1335
  // Pass 1: discover labels + compute sizes.
  let e1: i64 = assemble_pass(A, t)
  // Diagnostic: report how far pass-1 walked vs total.  Lets us see
  // whether the loop bailed (pos < src_len) or a label-table cap
  // was hit (n_labels at LABELS_CAP).
  nxasm_diag_pass1(A, src_len)
  if e1 != 0 { return -2 }
1343
  // Pass 2: emit bytes.
  A.pass = 2
  A.pos = 0
  A.cur_addr = 0
  A.out_pos = 0
  let e2: i64 = assemble_pass(A, t)
  if e2 != 0 { return -3 }
1351
  return A.out_pos
1353}
1354
1355
1356// Library only; self-test lives in nxasm_v2_test.nx.
nxasm_v2.nx source

`nxasm_v2.nx` source
