_gemm_i32_throughput_bench.nx

_gemm_i32_throughput_bench.nx -- pure-software GEMM i32 throughput. THE primary AI-workload baseline per the operator's cardinal of 2026-05-26: "lets use this system and how it runs ai as the test to see if we can optimize better than other systems like cuda using nishi from 0 up". General matrix-matrix multiply (GEMM) -- the operation that dominates the runtime of every transformer / FFN / attention layer in 2026-era LLMs. CUDA's killer feature is GEMM acceleration; if Nishi-silicon ever beats CUDA, this bench is the yardstick. Computes C = A * B for N x N i32 matrices, accumulating in i64. Runs ITERS iterations so wall-clock timing converts to GFLOPS: FLOPS = 2 * N^3 * ITERS / time_seconds (factor of 2 because each MAC = 1 multiply + 1 add) Today: pure-NishiLang loop, no SIMD, no AVX, no MUL widening intrinsics, no cache blocking. Expected ~50-200 MFLOPS on a modern x86_64. CUDA on H100: ~70 TFLOPS for INT8. So today we're ~350,000x slower than CUDA on this benchmark. That's the BASELINE. The silicon-feedback loop (M3 in ZERO_TO_ADVANCED.md) consumes this number + the per-PC cycle attribution from rv64im_min_sim (commit 4365e77) to identify what silicon-side acceleration would close the gap most efficiently: - SIMD i32 vector instructions - MAC fusion (multiply-add-accumulate as one cycle) - Systolic array (TPU/silicon-vendor style) - Sparse / quantized accelerators Each silicon decision gets a measured ROI number from THIS bench post-acceleration; the gap shrinks generation by generation. Returns: 0 (success); non-zero indicates setup failure.