code wiki / _hdl_build / _nvme_oplist_gate.nx

_nvme_oplist_gate.nx

buildroot/runtime/_hdl_build/_nvme_oplist_gate.nx

9633 B171 linesdepth 2pulls 2 transitivereach 0 importersview sourcekind gate/proof
docsdependenciesstructsconstsfunctions

about

_nvme_oplist_gate.nx -- CONSOLIDATION gate for X-DRV-W1: NVMe as a GENERIC op-list on the CANONICAL emitter nx_drv_proto_emit (NOT the parallel bespoke nx_drvgen). Proves the no-sprawl consolidation: (1) NVME -- the GENERIC nx_drv_proto_emit, driven by knowledge/specs/nvme_oplist_virt.spec alone (zero emitter change), authors an NVMe-class bring-up driver; the SOVEREIGN rv64 emu (+ the rv64im_min_nvme device model) runs it: CC.EN -> confirm CSTS.RDY -> bind ASQ/ACQ by base-address regs -> lay the 64B SQE -> ring the SQ-Tail doorbell -> device DMAs + posts the phase-tagged CQE -> driver reads NvmeCqPeek back == 0x12340001. Serial CONTAINS the golden "NVMEENASQSQECQ" + a clean SiFive halt (BOOTSOV verdict=GREEN). (2) DISTINCT -- the SAME emitter binary, driven by the virtio-blk op-list, yields a DIFFERENT golden; NVMe is a 3rd device class as just-a-spec, not virtio in disguise. (3) TAMPER x2 on the NVMe image: bump the device-base lui imm (byte 7) -> all MMIO targets a non-device address -> the VS identity verify fails -> the whole transcript collapses; bump the VS-expected li high byte (byte 15) -> the identity verify mismatches -> collapses. Each must drop the golden (the no-false-green handle; a no-op driver would be immune). Every verdict is a PRINTED marker off a REAL sovereign run, never an asserted GREEN; raw bytes are read SOVEREIGNLY (sys_read). NO qemu/gcc/openssl/python -- the sovereign emu IS the runtime; NVMe is a last-mile probe. Marker -> knowledge/status/driver_spec.log (NVMEOPGATE row). Sovereign orchestration (fork/dup3/execve/wait4). license_tier: ORIGINAL

dependencies 1 imports · 0 importers

nx_syscalls.nx _nvme_oplist_gate.nx

imports: nx_syscalls.nx

imported by: nobody (leaf or entry point)

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

main q_p sys_write sys_openat_append sys_mmap q_emit_run q_run1 sys_fork sys_openat_wr sys_dup3 sys_mmap ↻ sys_execve sys_exit sys_wait4 q_read sys_openat_rd sys_read sys_close sys_mmap ↻ q_buf_has q_strlen q_streq q_tamper sys_mmap ↻ q_read ↻ sys_openat_wr ↻ sys_write ↻ sys_close ↻ q_run1 ↻ q_buf_has ↻ q_run1 ↻ q_fp sys_write ↻ q_fn sys_mmap ↻ sys_write ↻ sys_now_realtime_sec sys_mmap ↻ sys_clock_gettime_real sys_close ↻

structs

none

consts

23const EMIT_ELF: *u8 = "_offc/nx_drv_proto_emit.elf"
24const SOV_ELF: *u8 = "_offc/nx_boot_run_sov.elf"

functions

26func q_p(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 }
called by 1: main calls 1: sys_write
27func q_fp(fd: i64, s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(fd,s,n); return 0 }
called by 1: main calls 1: sys_write
28func q_fn(fd: i64, v: i64) -> i64 { let bb: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m}; let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48;k=1}; while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1}; var i: i64=0; while i<k{bb[i]=t[k-1-i];i=i+1}; sys_write(fd,bb,k); return 0 }
called by 1: main calls 2: sys_mmapsys_write
31func q_run1(prog: *u8, a1: *u8, outpath: *u8) -> i64
52func q_read(path: *u8, buf: *u8, cap: i64) -> i64
62func q_buf_has(buf: *u8, n: i64, pat: *u8, pl: i64) -> i64
called by 2: q_emit_runq_tamper
74func q_strlen(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} return n }
called by 1: main
76func q_streq(a: *u8, b: *u8) -> i64
called by 1: main
85func q_emit_run(spec: *u8, out: *u8, goldout: *u8, gbuf: *u8, gcap: i64, serialpath: *u8) -> i64
called by 1: main calls 4: q_run1q_readsys_mmapq_buf_has
101func q_tamper(srcbin: *u8, pos: i64, golden: *u8, gn: i64, tampbin: *u8, serialpath: *u8) -> i64
117func main() -> i64