code wiki / _hdl_build / _timer_irq_gate.nx
_timer_irq_gate.nx
buildroot/runtime/_hdl_build/_timer_irq_gate.nx
about
_timer_irq_gate.nx -- gate for the TIMER-INTERRUPT (preemption mechanism) slice.
NO mocks: runs the REAL nx_timer_irq_emit (team AUTHORS the rv64 image + TABLE-COMPUTED
golden "BT"), RUNS it on the SOVEREIGN rv64 emu (PRIMARY: Nishi owns the runtime), asserts
the serial CONTAINS the golden (B=boot, T=timer-interrupt handler ran) AND a clean finisher
halt (BOOTSOV verdict=GREEN). Then a TAMPER: zero the mie.MTIE-enable immediate -> the CPU
never takes the timer trap -> the handler never runs -> 'T' disappears -> the gate MUST go RED
(proves the gate bites, not a rubber stamp -- the timer interrupt is REALLY what produces T).
Evidence -> knowledge/status/timer_irq.log (TIMERIRQGATE row). Sovereign orchestration.
license_tier: ORIGINAL
dependencies 1 imports · 0 importers
imports: nx_syscalls.nx
imported by: nobody (leaf or entry point)
call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown
structs
| none |
consts
| none |
functions
| 12 | func g_p(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 } |
| 13 | func g_fp(fd: i64, s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(fd,s,n); return 0 } |
| 14 | func g_fn(fd: i64, v: i64) -> i64 { let bb: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m}; let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48;k=1}; while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1}; var i: i64=0; while i<k{bb[i]=t[k-1-i];i=i+1}; sys_write(fd,bb,k); return 0 } |
| 16 | func g_run1(prog: *u8, arg1: *u8, outpath: *u8) -> i64 |
| 39 | func g_read(path: *u8, buf: *u8, cap: i64) -> i64 |
| 49 | func g_buf_has(buf: *u8, n: i64, pat: *u8, pl: i64) -> i64 called by 1: main |
| 62 | func main() -> i64 |