nx_attest_silicon.nx

nx_attest_silicon.nx -- per-chip trust declaration. Per [[feedback-captain-moroni-doctrine]] Phase M4 and [[feedback-reclamation-doctrine-captain-moroni]]: every supported chip declares its known threat surface (Intel ME, AMD PSP, Apple T2, Qualcomm baseband, vendor BMC) + the mitigations available against that surface + the resulting trust ceiling. This is the LOOKUP TABLE that turns the reclamation doctrine into runtime data: given a chip family, what xenocells need to be instantiated, what budget caps apply, what operations remain unsafe even after all mitigations are applied. Composes: nx_xenocell -- the threat surfaces listed here become xenocells the substrate instantiates nx_organism -- xenocells from attest_silicon get registered with the organism so they're counted in host pressure aggregation nx_budget -- trust ceiling influences how much RAM/VRAM budget the substrate will accept declarations for (low-trust hardware refuses big budgets) nx_reclaim -- the composed operation that consumes this attestation to produce a safety envelope V1 ships a hard-coded chip family enum + threat-surface bitmask + trust_score per family. V2 will read from a content-addressed chip-attestation database (peer-sharable so the community can extend coverage without recompiling substrate). Gap list (V1 honest perf verdict): - chip family enum is HARDCODED (V2 makes it data-driven) - no actual silicon probe to AUTO-DETECT chip family (the host OS's /proc/cpuinfo or DMI tables are queued; today the caller supplies the chip family ID) - mitigation_applied is a bitmask; partial application not representable (mitigation either applied or not) - sovereign-Nishi silicon entry is a stub genealogy_id: cardinal_2026-05-07_captain_moroni_doctrine +