nx_blob_store_mcu.nx

nx_blob_store_mcu.nx -- MCU-tier variant of blob_store class. EM-6 milestone of NISHI_ECOSYSTEM_EVOLUTION_ROADMAP.md. Same API shape as L0 nx_blob_store but with footprint tuned for MCU-class devices (capacity 4, max blob 256 bytes). Declared as variant of class `blob_store`, so the SA-arc selector can pick THIS for MCU-tier targets and the regular nx_blob_store for laptop-class+. This is the FIRST class to carry multiple variants (`blob_store` V1 + V1_MCU), exercising the cross-tier selection path the SA arc architecture promised but had no real test for until now. V1 footprint envelope: - Capacity: 4 entries (vs 256 in regular L0) - Max blob size: 256 bytes (vs 16 MiB in regular L0) - Index footprint: ~80 B struct + 4 * (32+8) = 240 B - Total RAM (excluding blob bodies): ~320 B - Blob bodies still mmap'd separately (caller-allocated) This fits comfortably on Arduino Uno (2 KB SRAM), STM32F0 family, nRF52 series, ESP8266, and most Cortex-M0+ devices. AVR backend (EM-10) will produce binary that consumes < 1 KB. API mirrors nx_blob_store with `_mcu` suffix to coexist without symbol collision. Future variant-resolver work can use the substrate's manifest system to dispatch by tier without caller awareness. genealogy_id: cardinal_2026-05-20_ecosystem_evolution + nx_blob_store_v1 lineage lineage_id: substrate_blob_store_mcu_v1 nx_capability_manifest: variant_class: blob_store variant_id: blob_store_v1_mcu_inline requires_isa: [rv32i, rv32imac, rv64imac, x86_64, cortex_m, armv7a, aarch64, avr] requires_syscalls: [mmap] requires_ram_min_b: 512 tier_floor: NX_TIER_INF_MCU tier_ceiling: NX_TIER_INF_MOBILE