nx_blocked_matmul.nx
buildroot/runtime/nx_blocked_matmul.nx
about
nx_blocked_matmul.nx -- attack the MEMORY-BANDWIDTH roof the AVX2 arc exposed: CACHE BLOCKING.
Naive GEMM re-streams ALL of Bt (N*K*4) for EVERY row of A -> at 1024^3, Bt=4MB >> L2, so it re-reads
from L3/DRAM M times = the bandwidth wall. i-BLOCKING keeps a panel of A rows (BI*K*4) resident in L2
and reuses each Bt row across the whole panel -> Bt DRAM traffic cut ~BI x. Same AVX2 __f32x8_dot kernel,
same result (bit-exact) -- ONLY the loop order / memory-access pattern changes. This is the lever that
makes AVX2's width actually pay off and lets multicore scale again. No hw writes (Rule 26).
expect_exit: 0 license_tier: ORIGINAL
dependencies 1 imports · 0 importers
imports: nx_syscalls.nx
imported by: nobody (leaf or entry point)
call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown
structs
| none |
consts
| 9 | const K_MAGIC_1024: i64 = 1024 |
| 10 | const K_MAGIC_1842560: i64 = 1842560 |
functions
| 12 | func bm_puts(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 } |
| 13 | func bm_num(v: i64) -> i64 { let b: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m;sys_write(1,"-" as *u8,1)} let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48 as u8;k=1} while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1} var i: i64=0; while i<k{b[i]=t[k-1-i];i=i+1} sys_write(1,b,k); return 0 } |
| 14 | func pack4(buf: *u8, idx: i64, bits: i64) -> i64 { buf[idx*4+0]=(bits) as u8; buf[idx*4+1]=(bits>>8) as u8; buf[idx*4+2]=(bits>>16) as u8; buf[idx*4+3]=(bits>>24) as u8; return 0 } called by 1: main |
| 17 | func naive_mm(pa: *u8, pbt: *u8, c: *i64, M: i64, N: i64, K: i64) -> i64 called by 1: main |
| 29 | func blocked_mm(pa: *u8, pbt: *u8, c: *i64, M: i64, N: i64, K: i64, BI: i64) -> i64 called by 1: main |
| 51 | func main() -> i64 |