code wiki / _hdl_build / nx_boot_run_sov.nx

nx_boot_run_sov.nx

buildroot/runtime/_hdl_build/nx_boot_run_sov.nx

5991 B107 linesdepth 6pulls 17 transitivereach 0 importersview sourcekind tooltopic boot
docsdependenciesstructsconstsfunctions

about

nx_boot_run_sov.nx -- the SOVEREIGN boot runtime. Loads an emitter-authored rv64 flat binary into the Nishi-owned rv64 emulator (rv64im_min_sim + its 16550 UART / SiFive finisher / M-mode CSR / CLINT / virtio / NVMe / Sv39-MMU device models) and RUNS it -- the kernel boots on OUR silicon model, not qemu. qemu stays a pure ALIGNMENT cross-check, never the runtime. ★FIXED 2026-07-31 (debt 1785517037): this runner used to decide its verdict from `halted && halt_code==0` ALONE and NEVER READ THE SERIAL IT HAD JUST CAPTURED. Proven by tamper: an image whose Sv39 walk was broken emitted "...TICK TX" -- the paging phase DEAD -- and BOOTSOV still returned verdict=GREEN exit=0; clearing medeleg dropped the USER marker and it still returned GREEN. A runner that returns GREEN on a boot it can see is broken is not a check. It now compares the captured transcript against the artifact's golden and goes RED on mismatch. Backwards-compatible BY CONSTRUCTION: an image with NO golden behaves exactly as before (halt-only verdict) and says so, so nothing that boots a golden-less payload changes. nx_boot_run_sov [binpath] [goldpath] exit 0 = booted + clean halt + (golden matched or absent); 1 = otherwise Boot-and-capture comes from the shared nx_bootcap primitive so this runner, the gate, the census and the adoption ruler cannot disagree about what "booting the image" means. Sovereign: the emulator IS the runtime. license_tier: ORIGINAL

dependencies 1 imports · 0 importers

nx_bootcap.nx nx_boot_run_sov.nx

imports: nx_bootcap.nx

imported by: nobody (leaf or entry point)

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

main bootcap_load sys_read_file sys_openat_rd sys_lseek sys_mmap sys_read sys_close br_p bootcap_run nx_rv64im_rf_init nx_rv64im_csr_init nx_clint_init nx_uart_init nx_virtio_init nx_virtio_reset_storage nx_virtio_init_net nx_virtio_reset_storage ↻ nx_nvme_init nx_nvme_reset_storage nx_nndev_init nx_nndev_reset nx_mmu_init nx_mmu_reset nx_rv64im_sim_init nx_rv64im_sim_attach_virti nx_rv64im_sim_attach_virti nx_rv64im_sim_attach_nvme nx_rv64im_sim_attach_nndev nx_rv64im_sim_attach_mmu nx_rv64im_sim_run nx_rv64im_sim_step nx_clint_tick nx_clint_update_mtip nx_rv64im_csr_tick_mcycle nx_clint_mtip_get nx_rv64im_csr_read nx_csr_addr_to_slot nx_rv64im_sim_take_trap nx_rv64im_csr_read ↻

structs

none

consts

21const BR_BIN: *u8 = "runtime/_hdl_build/_boot_nishi_virt.bin"
22const BR_BIN_ALT: *u8 = "_boot_nishi_virt.bin"
23const BR_GOLD_ALT: *u8 = "runtime/_hdl_build/_boot_nishi_virt.bin.gold"
24const BR_TX_CAP: i64 = 4096
25const BR_LOG: *u8 = "knowledge/status/boot_stub.log"

functions

27func br_p(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 }
called by 1: main
28func br_fp(fd: i64, s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(fd,s,n); return 0 }
called by 1: main
29func br_fn(fd: i64, v: i64) -> i64 { let bb: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m}; let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48;k=1}; while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1}; var i: i64=0; while i<k{bb[i]=t[k-1-i];i=i+1}; sys_write(fd,bb,k); return 0 }
called by 1: main
31func br_eq(a: *u8, an: i64, b: *u8, bn: i64) -> i64
called by 1: main
38func main(argc: i64, argv: *i64) -> i64