nx_compute_mt.nx
buildroot/runtime/nx_compute_mt.nx
about
nx_compute_mt.nx -- walking up the COMPUTE wall toward physics: MULTICORE matmul (the ~20x lever).
The compute physics grade (nx_compute_ladder) found the sovereign matmul ~5000x below the silicon f32
peak -- but the peak assumes ALL cores; the matmul used ONE. Multicore is the biggest single lever and
needs NO compiler surgery: fork N workers over a SHARED-memory C, each computing a disjoint row band.
This measures single-thread vs N-thread on the SAME problem, proves the parallel result is bit-identical
to the serial one (correctness across processes), and reports the speedup + how much of the physics gap it
closes. Sovereign: sys_fork + sys_mmap_shared + sys_wait4 + nx_f32_hw SSE f32.
KAT: parallel result == serial (bit-exact); multicore is faster; speedup + closed gap reported.
HONEST: this is the multicore lever only; packed-SIMD (4-8x) + FMA (2x) + blocking still remain (deeper,
compiler-side). No hw writes (Rule 26). expect_exit: 0 license_tier: ORIGINAL
dependencies 2 imports · 0 importers
imports: nx_f32_hw.nxnx_syscalls.nx
imported by: nobody (leaf or entry point)
call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown
structs
| none |
consts
| 13 | const K_MAGIC_1842560: i64 = 1842560 |
functions
| 15 | func mt_puts(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 } |
| 16 | func mt_num(v: i64) -> i64 { let b: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m;sys_write(1,"-" as *u8,1)} let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48 as u8;k=1} while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1} var i: i64=0; while i<k{b[i]=t[k-1-i];i=i+1} sys_write(1,b,k); return 0 } |
| 19 | func mm_band(a: *i64, b: *i64, c: *i64, sz: i64, w: i64, nw: i64) -> i64 called by 1: main |
| 37 | func main() -> i64 |