nx_compute_opt2.nx

nx_compute_opt2.nx -- compute wall, step 2: stack the SAFE levers (cache locality + more cores). The naive GEMM inner loop reads B[l*n+j] -- a COLUMN walk, stride n, a cache miss per access. Transpose B once (Bt[j*k+l]=B[l*n+j]) so the inner loop reads CONTIGUOUSLY (stride 1) = the cache-blocking lever. Then run that cache-friendly kernel across all cores (fork + shared mem). Both pure-NishiLang, no compiler surgery. Measures naive-1-thread vs transposed-1-thread (the cache lever alone) vs transposed-multicore (cache + cores), proves every variant is bit-identical, and reports the cumulative gap reduction toward the silicon f32 peak. Sovereign: nx_f32_hw SSE + sys_fork/sys_mmap_shared/sys_wait4. KAT: all variants bit-identical; transposed faster than naive; multicore faster still. HONEST: cache + cores levers only; packed-SIMD (4-8x) + FMA (2x) still remain (compiler-side). No hw writes (Rule 26). expect_exit: 0 license_tier: ORIGINAL