nx_dispatcher.nx

nx_dispatcher.nx -- hardware-aware op routing. Per CARDINAL [[feedback-conductor-heterogeneous-compute-no-second-class- resources]]: ops dispatch hardware-aware -- matmul on GPU when operands are in VRAM, activations on CPU SIMD when data lives in RAM, no PCIe round-trips for tiny ops. REFUSES the "everything goes to GPU" pattern. CONDUCTOR ARC ROLE: this is PHASE C of the conductor arc documented in nx_placement.nx. Composition stack: A) nx_placement.nx -- NxPlacedTensor with placement tag (MMAP/ OWNED/VRAM/NETWORK). SHIPPED. B) nx_gguf_load_lazy.nx -- lazy GGUF load returning NxPlacedTensor. SHIPPED. C) nx_dispatcher.nx -- per-op hardware routing. THIS BRICK. D) nx_resource_arbiter.nx -- multi-tier budget tracking. THIS SESSION. E) async DMA primitives. Queued. Integration: the bridge function nx_di_req_from_placed_inputs() reads NxPlacedTensor.placement to populate this primitive's inputs_on_gpu/cpu/cold accounting, so callers using the existing nx_placement substrate can compose without forking. V1 ships a sealed op-kind enum + per-op cost model + dispatch decision that picks the cheapest backend given the placement of inputs (uses [[nx_tensor_placement]] semantics: tier index 0=fastest, 7=coldest). Cost model is intentionally simple Q10: BACKEND_COST_PER_BYTE * total_input_bytes + TRANSFER_COST * misplaced_bytes. Refinement (cache effects, batch size, kernel launch overhead) deferred.