nx_drvgen.nx

SUPERSEDED 2026-06-13 (no-sprawl consolidation): the CANONICAL driver-from-spec emitter is the op-list-driven nx_drv_proto_emit.nx -- there a NEW device class is a NEW op-list SPEC with ZERO emitter change (the protocol step-sequence is DATA). nx_drvgen hardcodes the NVMe stage ORDERING in code (a per-class emitter), which the X-DRV-W1 council flagged as a generality dilution. NVMe is now carried as an op-list spec: knowledge/specs/nvme_oplist_virt.spec, gate-proven by _nvme_oplist_gate (knowledge/status/driver_spec.log::NVMEOPGATE verdict=GREEN). nx_drvgen + nx_driver_shapes are KEPT as the regression reference (NVMEGATE stage=B), not extended. New work -> add an op-list spec to nx_drv_proto_emit, NOT a new bespoke emitter. nx_drvgen.nx -- the GENERIC driver-image author for the 2nd device class (X-DRV-W1 stage B). A NEW device class IS A SPEC FILE: nx_drvgen reads an NVMe-class controller spec (knowledge/specs/nvme_admin_enable_virt.spec) and AUTHORS a bare-metal rv64 flat image whose driver performs the REAL NVMe controller bring-up by routing EVERY byte through the SAME device-agnostic shape library (nx_driver_shapes: WIRE_TLV / COMMAND_QUEUE / STATE_MACHINE / STRUCT_WALK) that re-emits the virtio image byte-identically in PROOF-1. The shape library knows ZERO NVMe -- the controller identity, offsets, queue bases, SQE/CQE layout, and the phase-tag KAT all arrive from the spec. So the NVMe driver's distinctness comes from spec DATA, not from any virtio code path. The driver the image runs (NVMe 1.4 base spec bring-up subset): verify VS == 0x00010400 (1.4.0) -> emit "VIO-NVME " write CC.EN=1, POLL CSTS until RDY set (STATE_MACHINE poll loop) -> emit "EN " <-- a REAL backward branch (the structural fingerprint virtio's straight-line handshake lacks) bind AQA + ASQ/ACQ base-address regs, read ASQ_LO back + verify -> emit "RDY " lay the 64-byte SQE (opcode/CID/CDW10) into ASQ_base (STRUCT_WALK) -> emit "ASQ " ring the SQ-Tail doorbell (the device posts the phase-tagged CQE) -> emit "SQE " POLL the CQE phase bit in ACQ RAM, read NvmeCqPeek back + verify -> emit "CQ\n" <-- a SECOND backward branch (the CQE phase-tag poll); the verify is the tamper canary write the SiFive finisher -> clean halt. Any verify that fails BRANCHES PAST the rest of the bring-up straight to the finisher, so the transcript loses its tail (the " CQ" canary, etc.) -- the gate's tamper test exploits this. nx_drvgen <specpath> -> writes the flat image to the spec's `out` + the golden to <out>.gold VERDICT log -> knowledge/status/virtio_blk.log (DRVGEN rows). Sovereign: syscalls only, no gcc/.sh. NVMe/PCI is a last-mile interop PROBE + measuring stick to EXCEED, never a substrate -- the emitted driver + shapes are Nishi-native. license_tier: ORIGINAL