code wiki / _hdl_build / nx_emu_x86_dev_test.nx
nx_emu_x86_dev_test.nx
buildroot/runtime/_hdl_build/nx_emu_x86_dev_test.nx
about
nx_emu_x86_dev_test.nx -- x86 full-system ladder R7: DEVICE MODELS (the 16550 UART serial console).
x86 talks to devices over an I/O PORT space (in/out instructions). COM1's 16550 UART sits at port
0x3F8; writing a byte to it (the THR) transmits a serial character -- the console a kernel prints
through (the x86 twin of the rv64 UART that emitted NISHI). io_out() models the port dispatch +
the UART. KAT: a "print" routine writes "NISHI-X86" to 0x3F8 -> it lands in the UART tx buffer; a
write to a non-UART port (0x60 keyboard) does NOT.
HONEST SCOPE: the UART tx device + port dispatch; wiring io_out into the emu's OUT-instruction
decode (EE / E6) + timer (PIT/APIC) + disk (ATA/AHCI/virtio) models = R7 rung-2+. R8 = an x86
kernel that boots through R1-R7 end-to-end. No hardware writes (Rule 26). expect_exit: 0 license_tier: ORIGINAL
dependencies 1 imports · 0 importers
imports: nx_syscalls.nx
imported by: nobody (leaf or entry point)
call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown
structs
| none |
consts
| 12 | const UART_COM1: i64 = 0x3F8 |
functions
| 14 | func dv_puts(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 } |
| 15 | func dv_num(v: i64) -> i64 { let b: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m;sys_write(1,"-" as *u8,1)} let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48 as u8;k=1} while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1} var i: i64=0; while i<k{b[i]=t[k-1-i];i=i+1} sys_write(1,b,k); return 0 } |
| 16 | func dv_beq(a: *u8, b: *u8, n: i64) -> i64 { var i: i64=0; while i<n { if a[i]!=b[i] { return 0 } i=i+1 } return 1 } called by 1: main |
| 19 | func io_out(uart_tx: *u8, uart_len: *i64, port: i64, byte: i64) -> i64 called by 1: main |
| 24 | func main() -> i64 |