code wiki / _hdl_build / nx_emu_x86_paging_test.nx
nx_emu_x86_paging_test.nx
buildroot/runtime/_hdl_build/nx_emu_x86_paging_test.nx
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nx_emu_x86_paging_test.nx -- x86 full-system ladder R6: PAGING (long-mode 4-level page walk).
Long mode translates a 48-bit virtual address through 4 tables (512 entries each, 8-byte entries):
VA[47:39]=PML4 idx -> VA[38:30]=PDPT idx -> VA[29:21]=PD idx -> VA[20:12]=PT idx -> +VA[11:0] off
Each entry holds the next table's (or the page's) 4KB-aligned base in bits[63:12] + flags (bit0=present).
This models that walk over an in-RAM page-table tree (the x86 twin of the rv64 SV39 MMU we have).
KAT: tables mapping VA 0x1000->PA 0x40000 and 0x2000->0x50000; translate + offset; unmapped -> fault.
HONEST SCOPE: 4KB pages, present bit; large pages / A-D bits / TLB / permission faults = refinements.
R7 = device models (16550 UART/timer/disk). No hardware writes (Rule 26). expect_exit: 0 license_tier: ORIGINAL
dependencies 1 imports · 0 importers
imports: nx_syscalls.nx
imported by: nobody (leaf or entry point)
call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown
structs
| none |
consts
| none |
functions
| 11 | func pg_puts(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 } |
| 12 | func pg_num(v: i64) -> i64 { let b: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m;sys_write(1,"-" as *u8,1)} let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48 as u8;k=1} while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1} var i: i64=0; while i<k{b[i]=t[k-1-i];i=i+1} sys_write(1,b,k); return 0 } |
| 14 | func pg_wr(mem: *u8, addr: i64, v: i64) -> i64 { var i: i64=0; while i<8 { mem[addr+i]=((v>>(i*8)) & 0xff) as u8; i=i+1 } return 0 } called by 1: main |
| 15 | func pg_rd(mem: *u8, addr: i64) -> i64 { var v: i64=0; var i: i64=0; while i<8 { v = v | ((mem[addr+i] as i64) << (i*8)); i=i+1 } return v } called by 1: pg_walk |
| 18 | func pg_walk(mem: *u8, cr3: i64, va: i64) -> i64 |
| 38 | func main() -> i64 |