nx_f16.nx

nx_f16.nx -- IEEE 754 binary16 (half-precision float) bits-up. L2 of the bits-up numeric tower (see docs/NISHI_BITS_UP_NUMERIC_TOWER_ROADMAP.md). Substrate-side IEEE 754 conformant f16 arithmetic on i64 backend. No libm, no soft-float linker stubs, no compiler-builtin lowerings. Bit layout (IEEE 754-2019): bit 15: sign (1 = negative) bits 14..10: exponent (biased by 15; 0 = subnormal/zero; 31 = inf/NaN) bits 9..0: mantissa (10 bits; implicit leading 1 for normal) Real value = (-1)^sign * 2^(exp - 15) * (1.mantissa) for normal = (-1)^sign * 2^-14 * (0.mantissa) for subnormal Storage convention in NishiLang: an f16 value is stored in the LOW 16 bits of an i64. The high 48 bits MUST be zero for the extraction macros to work. Pack/unpack helpers enforce this. Operations implemented in this brick: nx_f16_classify(x) -- returns NX_F16_CLS_* (zero / normal / subnormal / inf / nan) nx_f16_is_nan(x) nx_f16_is_inf(x) nx_f16_neg(x) -- flip sign bit nx_f16_abs(x) -- clear sign bit nx_f16_eq(a, b) -- IEEE 754 equality (NaN != NaN) nx_f16_add(a, b) -- IEEE 754 addition with round-to-nearest-even nx_f16_sub(a, b) -- a + (-b) nx_f16_mul(a, b) -- IEEE 754 multiply (round-to-nearest-even) nx_f16_from_q10(q) -- Q10 i64 -> f16 (used at substrate boundary) nx_f16_to_q10(x) -- f16 -> Q10 i64 (composes _gguf_f16_to_q10 from nx_gguf_load.nx, included as the canonical decoder used by the GGUF stack today) Future bricks compose: - nx_f16_div, nx_f16_sqrt, nx_f16_fma (L2 follow-on, queued) - nx_bf16.nx (L3 brain-float-16) - nx_f32.nx (L4 single-precision; ML inference primary target) - nx_f64.nx (L5 double-precision)