nx_f32_conv2d.nx
buildroot/runtime/nx_f32_conv2d.nx
about
nx_f32_conv2d.nx -- software-f32 multi-channel 2D convolution (NCHW), the R3 vision-op re-tier.
sd-server -> Nishi migration, rung 3: the existing `nx_conv2d.nx` is i64 Q10, HARDCODED 3x3, stride-1,
pad-1, and has only ever run on identity weights. This is the same direct convolution in the sovereign
software-f32 tier (`nx_f32_*`, IEEE-754-in-i64, gated) AND generalized to arbitrary KH/KW + stride + pad,
so it covers everything the DiT/VAE use: 1x1 projections, 3x3 ResBlock convs, and stride-2 downsamples.
Real dequantized GGUF weights flow through it.
Tensors: flat `*i64` of f32 bit-patterns. input [N,C_in,H,W], weight [C_out,C_in,KH,KW], bias [C_out]
(nullable=0), out [N,C_out,OH,OW] with OH=(H+2*pad-KH)/stride+1, OW=(W+2*pad-KW)/stride+1. Caller
allocates out for those dims. Zero-padding. In-place NOT supported (in != out). Composes only gated
primitives nx_f32_add / nx_f32_mul. No libm, no Q-scaling (f32 multiply needs no rescale).
license_tier: ORIGINAL
dependencies 3 imports · 13 importers
diagram shows first 10 each side; +0 more imports, +3 more importers in the complete lists below.
imports: nx_syscalls.nxnx_f32.nxnx_f32_cvt.nx
imported by: nx_conv_bwd_stride_gate.nxnx_f32_bn_fold_gate.nxnx_f32_conv2d_fast_gate.nxnx_f32_conv2d_grouped_gate.nxnx_f32_conv_train_gate.nxnx_f32_resblock.nxnx_f32_vae_decode_tiny.nxnx_pose_backprop_gate.nxnx_pose_cnn.nxnx_pose_distill_gate.nxnx_pose_student_distill.nxnx_vitpose_forward.nxnx_vitpose_patchembed.nx
call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown
structs
| none |
consts
| 18 | const NX_F32CV_OK: i64 = 0 |
| 19 | const NX_F32CV_ERR_BAD_ARGS: i64 = 4 |
functions
| 21 | func nx_f32_conv2d_forward(input: *i64, N: i64, C_in: i64, H: i64, W: i64, |
| 90 | func main() -> i64 |