nx_f32_dit_block_simd.nx
buildroot/runtime/nx_f32_dit_block_simd.nx
about
nx_f32_dit_block_simd.nx -- SANA-DiT block with SIMD (__f32x8_dot) projections: the end-to-end fast unit.
Bridges the two layouts: activations flow as i64-f32 for the elementwise/attention ops; before each
projection they PACK to 4-byte f32 (weights pre-packed once) so dbl_linear_simd runs the compute bulk on
AVX vmulps (~10x, measured in nx_f32_linear_simd). Same block as nx_f32_dit_block_linear; only the linears
change. adaLN-Zero gate (gt=0 => out==x) proves the wiring survives the layout bridging. Scratch mmap'd
inside (block called a handful of times, not a hot loop) to keep the arg list small.
license_tier: ORIGINAL
dependencies 6 imports · 0 importers
imports: nx_syscalls.nxnx_le.nxnx_f32.nxnx_f32_div.nxnx_f32_cvt.nxnx_f32_activations.nx
imported by: nobody (leaf or entry point)
call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown
structs
| none |
consts
| none |
functions
| 16 | func dsb_phi(v: i64) -> i64 |
| 22 | func dsb_pack(src: *i64, dst: *u8, count: i64) -> i64 |
| 28 | func dsb_linear_simd(inp_p: *u8, W_p: *u8, out: *i64, n: i64, id: i64, od: i64) -> i64 |
| 46 | func dsb_modulate(x: *i64, sc: *i64, sh: *i64, out: *i64, n: i64, D: i64) -> i64 |
| 56 | func dsb_linattn(Q: *i64, K: *i64, V: *i64, n: i64, D: i64, out: *i64, S: *i64, z: *i64) -> i64 |
| 91 | func dsb_gate_res(x: *i64, y: *i64, gt: *i64, out: *i64, n: i64, D: i64) -> i64 |
| 101 | func nx_f32_dit_block_simd(x: *i64, n: i64, D: i64, dff: i64, |
| 149 | func main() -> i64 |