nx_f32x4_matmul_gate.nx
buildroot/runtime/nx_f32x4_matmul_gate.nx
about
nx_f32x4_matmul_gate.nx -- PROVES the packed-SIMD compute lever end-to-end.
The new __f32x4_dot intrinsic (added through nx_parse -> nx_ir(reuse ir_emit_f32_binop) -> OP_F32X4_DOT
-> x86 codegen movups+mulps+scalar-hsum -> nxasm packed encoding) does 4 f32 multiplies in ONE mulps
instruction. This builds the SAME matmul two ways -- scalar (__f32_mul/__f32_add, one MAC/instr) and
packed (__f32x4_dot, 4 MAC/mulps) -- and (1) verifies they agree BIT-EXACT (small-int f32 so the
summation order cannot change the result), (2) checks a known-answer dot, and (3) MEASURES the speedup.
This is the top item on the autonomous research queue: compute was ~469x off the silicon floor and packed
SIMD is the decisive lever. Honest: per-4 horizontal-sum is overhead; a vector-accumulating kernel would
approach the full 4x -- this first packed kernel measures whatever it measures, no overclaim.
No hw writes (Rule 26). expect_exit: 0 license_tier: ORIGINAL
dependencies 2 imports · 0 importers
imports: nx_syscalls.nxnx_gate_verdict.nx
imported by: nobody (leaf or entry point)
call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown
structs
| none |
consts
| none |
functions
| 14 | func fx_puts(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 } |
| 15 | func fx_num(v: i64) -> i64 { let b: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m;sys_write(1,"-" as *u8,1)} let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48 as u8;k=1} while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1} var i: i64=0; while i<k{b[i]=t[k-1-i];i=i+1} sys_write(1,b,k); return 0 } |
| 18 | func pack4(buf: *u8, idx: i64, bits: i64) -> i64 called by 1: main |
| 27 | func scalar_mm(sa: *i64, sb: *i64, sc: *i64, M: i64, N: i64, K: i64) -> i64 called by 1: main |
| 41 | func packed_mm(pa: *u8, pb: *u8, pc: *i64, M: i64, N: i64, K: i64) -> i64 called by 1: main |
| 56 | func main() -> i64 |