nx_f32x8_matmul_gate.nx
buildroot/runtime/nx_f32x8_matmul_gate.nx
about
nx_f32x8_matmul_gate.nx -- PROVES the AVX2 8-wide lever past SSE 4-wide.
Three matmuls, same data: scalar (__f32_mul, 1 MAC/instr) vs SSE packed (__f32x4_dot, 4) vs AVX2 packed
(__f32x8_dot, 8 -- vmovups+vmulps 256-bit via .byte VEX, proven nxasm_vex_kat 7/7). Verifies all three
agree BIT-EXACT (small-int f32 -> order-independent) + a known-answer dot + MEASURES both packed speedups.
The AVX2 rung is the gating compute lever for racing sdcpp. Honest: vextractf128+hsum per 8 is overhead;
a vector-accumulating FMA kernel approaches the full 8x -- this first AVX2 kernel measures what it measures.
No hw writes (Rule 26). expect_exit: 0 license_tier: ORIGINAL
dependencies 2 imports · 0 importers
imports: nx_syscalls.nxnx_gate_verdict.nx
imported by: nobody (leaf or entry point)
call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown
structs
| none |
consts
| none |
functions
| 11 | func gx_puts(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 } |
| 12 | func gx_num(v: i64) -> i64 { let b: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m;sys_write(1,"-" as *u8,1)} let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48 as u8;k=1} while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1} var i: i64=0; while i<k{b[i]=t[k-1-i];i=i+1} sys_write(1,b,k); return 0 } |
| 13 | func pack4(buf: *u8, idx: i64, bits: i64) -> i64 { buf[idx*4+0]=(bits) as u8; buf[idx*4+1]=(bits>>8) as u8; buf[idx*4+2]=(bits>>16) as u8; buf[idx*4+3]=(bits>>24) as u8; return 0 } called by 1: main |
| 15 | func mm_scalar(sa: *i64, sb: *i64, c: *i64, M: i64, N: i64, K: i64) -> i64 called by 1: main |
| 24 | func mm_x4(pa: *u8, pb: *u8, c: *i64, M: i64, N: i64, K: i64) -> i64 called by 1: main |
| 35 | func mm_x8(pa: *u8, pb: *u8, c: *i64, M: i64, N: i64, K: i64) -> i64 called by 1: main |
| 47 | func main() -> i64 |