nx_f32x8_range_gate.nx
buildroot/runtime/nx_f32x8_range_gate.nx
about
nx_f32x8_range_gate.nx -- validate a VECTOR-ACCUMULATOR range dot
(__f32x8_fma across the whole k + ONE __f32x8_hsum) vs the current
__f32x4_dot loop (hsum every 4).
The matmul cached path (_lw_dot_task) uses __f32x4_dot, which does a
horizontal sum per 4 lanes (~2 uops/MAC = no better than scalar --
measured 3x this arc). The proper SIMD keeps an 8-wide accumulator
in a register/memory across the reduction and hsums ONCE. Both
intrinsics already exist; this gate proves (a) they agree bit-exact
in the exact-int regime and (b) the range dot is faster.
Checks:
1 f32x8 range dot == __f32x4_dot loop, bit-exact (exact ints)
2 range dot >= floor x faster over many reps at k=896
lineage_id: f32x8_range_gate_v1
dependencies 4 imports · 0 importers
imports: nx_syscalls.nxnx_f32.nxnx_f32_cvt.nxnx_fmt.nx
imported by: nobody (leaf or entry point)
call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown
structs
| none |
consts
| 23 | const RK: i64 = 896 // Qwen hidden = a real reduction dim (div by 8) |
| 24 | const RREPS: i64 = 40000 |
| 25 | const RFLOOR_X100: i64 = 150 |
functions
| 27 | func rg_st4(p: *u8, idx: i64, bits: i64) -> i64 called by 1: main |
| 34 | func rg_ld4(p: *u8, off: i64) -> i64 called by 1: dot_x8_range |
| 39 | func dot_x4(a: *u8, b: *u8, count: i64) -> i64 called by 1: main |
| 53 | func dot_x8_range(a: *u8, b: *u8, count: i64, acc: *u8) -> i64 |
| 73 | func rg_nl() -> i64 { fmt_puts("\n" as *u8); return 0 } |
| 75 | func main() -> i64 |