code wiki / _hdl_build / nx_hwtest_census.nx

nx_hwtest_census.nx

buildroot/runtime/_hdl_build/nx_hwtest_census.nx

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nx_hwtest_census.nx -- the HARDWARE-TEST-READINESS census: can we test NishiOS across LOTS of hardware (real) and on HYPOTHETICAL Nishi hardware? Grades each capability HAVE / PARTIAL / MISSING, grounded on a REAL organ (have_file -- liar-killed: a capability counts only if its organ actually exists on disk). The PARTIAL+MISSING rows ARE the roadmap. Grounded by: the SOTA critic (nx_ecosystem_maturity_rollup: kernel->composed-bootable-image-UEFI, silicon->PnR- bitstream-ULX3S-boot) + the researcher (our FPGA-BOOT SIMULATOR grounded ladder + FPGA/HDL/watchdog/CI corpus). expect_exit: 0 Sovereign: nx_syscalls. NEVER-BRICK: read-only census, writes 0 hardware state.

dependencies 2 imports · 0 importers

imports: nx_syscalls.nxnx_g_puts_lib.nx

imported by: nobody (leaf or entry point)

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

structs

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consts

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functions

10	func g_pn(v: i64) -> i64 { let b: *u8=sys_mmap(28); var x: i64=v; if x==0{b[0]=48;sys_write(1,b,1);return 0} var d: i64=0; var y: i64=x; while y>0{d=d+1;y=y/10} var i: i64=d-1; y=x; while i>=0{b[i]=(48+(y%10)) as u8;y=y/10;i=i-1} sys_write(1,b,d); return 0 } called by 1: main calls 2: sys_mmap sys_write
11	func ck(name: u8, c: i64) -> i64 { if c==1 { g_puts(" PASS " as u8) } else { g_puts(" FAIL " as u8) } g_puts(name); g_puts("\n" as u8); return c } called by 1: main calls 1: g_puts
12	func have(path: *u8) -> i64 { let fd: i64=sys_openat_rd(path); if fd<0 { return 0 } sys_close(fd); return 1 } called by 1: hw_row calls 2: sys_openat_rd sys_close
13	func hw_row(cap: u8, organ: u8, grade: i64, note: *u8) -> i64 called by 1: main calls 2: have g_puts
19	func main() -> i64 calls 8: g_puts hw_row g_pn ck sys_openat_append sys_write+2