nx_isa_cortexm_gate.nx

nx_isa_cortexm_gate.nx -- THE ARMv7-M / Cortex-M CONFORMANCE RULER. WHY IT EXISTS: nx_emu_cortexm.nx has claimed "we emulate Cortex-M" since it was written and had NEVER been run by anything. nx_isa_conform_gate measures five of the estate's ten sovereign emulators and names cortexm in its own UNMEASURED list. This organ closes that row for cortexm alone, in its own file, so two seats working two architectures cannot clobber one shared source. THE LAW: expectations come FROM THE ARMv7-M ARCHITECTURE REFERENCE MANUAL -- encodings out of the Thumb instruction tables, results out of the operation pseudocode -- never from reading the emulator and writing down what it happens to do. Reading the decoder is allowed for exactly one purpose: learning which classes are IMPLEMENTED versus MISSING, so a gap is named rather than mistaken for a wrong answer. Calibrating the ruler to the subject is the one failure that makes every green here worthless. WHAT READING THE DECODER FOUND, AND WHAT WAS DONE ABOUT IT (2026-09-03): the emulator implemented NO conditional branch, NO unconditional branch, NO CMP in either form, and carried ONE flag (C) with no N, Z or V. A machine that cannot take a branch cannot run a loop, so more than half of these KATs were unrunnable by construction. The gap was CLOSED in nx_emu_cortexm.nx rather than reported -- full NZCV off one shared ARM adder, the condition-code table, B-cond, B, CBZ/CBNZ, the immediate add/sub forms, the whole data-processing register block, the shifter, byte/halfword access, SP- and PC-relative addressing. Every KAT below that exercises one of those was RED before that work and is GREEN after it; that transition is the only evidence that this gate can fire at all. FIVE OUTCOMES, NEVER ONE: PASS ran and matched the manual-derived expectation WRONG-ANSWER ran to completion and computed the wrong value UNSUPPORTED hit an instruction class the emulator does not implement RAN-OFF-END the interpreter loop ended without reaching an exit FAULT bad PC, out-of-range fetch, or the step budget Collapsing these into "FAIL" is what makes a gap unactionable: an unimplemented instruction class and a miscomputed result need OPPOSITE fixes. THE EXIT-STATUS MASK IS A REAL HAZARD AND IS DESIGNED AROUND. Cortex-M here halts on BKPT with result = r0 & 0xff, so every legitimate answer is 0..255 and the three negative sentinels can never collide with one -- but two KATs whose right and wrong answers differ only above bit 7 would be indistinguishable. Each expectation below