nx_isa_manager.nx

nx_isa_manager.nx -- THE MASTER ISA MANAGER. WHAT IT IS: not another conformance gate. The gates measure ONE architecture each and answer "does this emulator obey its manual". This organ measures THE POPULATION and answers a different question: of every ISA the estate has declared in scope, which ones does anything at all measure, which have an emulator nobody rules on, which are declared and untouched, and what is the next actionable name in each of those classes. THE DENOMINATOR IS PUBLISHED. knowledge/isa_targets.conf is the population and it is READ, never inferred. A coverage ratio whose denominator is "the ISAs I happened to think of" flatters itself by omission; 14 of 122 is an honest number and 14 of 14 is not. impl AND ext ROWS ARE NOT TARGETS AND ARE EXCLUDED FROM EVERY EMITTER/EMULATOR RATIO. An impl row is a HOST that implements another row's ISA (Phytium implements aarch64) and an ext row is an EXTENSION of a base ISA (SVE extends aarch64). Counting either in a codegen ratio double-counts the base ISA and inflates the number in the one direction nobody audits. They get their own named state, NOT-A-TARGET, so they are visible and excluded at the same time. HOW A NEW ISA JOINS -- NO EDIT TO THIS ORGAN, EVER: 1. add a row to knowledge/isa_targets.conf. It reads DECLARED-ONLY. 2. write buildroot/runtime/nx_emu_<id>.nx. It reads EMULATOR-ONLY. 3. write buildroot/runtime/nx_isa_<id>_gate.nx, or import nx_emu_<id>.nx from nx_isa_conform_gate.nx. It reads GATE-PRESENT-UNRUN. 4. let that gate bank "<id> <passed>" into knowledge/status/isa_<id>.ratchet, or into the core gate's shared knowledge/status/isa_conform.ratchet. It reads MEASURED-GREEN. If the organs are already named something other than the conf id, add ONE row to knowledge/isa_emu_alias.conf. That file is DATA and the manager reports how many rows it used and names any alias whose id is not in the population, because an alias for an undeclared id is a typo that silently hides a target. DISCOVERY IS A PROBE, NOT A LIST. There is no array of architecture