code wiki / _hdl_build / nx_isa_spec.nx
nx_isa_spec.nx
buildroot/runtime/_hdl_build/nx_isa_spec.nx
about
nx_isa_spec.nx -- SPEC-DRIVEN instruction encoder (multi-arch). The capability
that removes the last hand-written piece of the machine-code generator: instead
of a bespoke bit-twiddling function per instruction, there is ONE generic
assembler per FORMAT (the bit layout), and each instruction is pure DATA --
{format, opcode/base, funct3, funct7} lifted straight from the ISA manual. The
team authors a new instruction by adding a data row, not by writing encoder code.
Covers RV64 (R / I / I-shift / fixed) and AArch64 (MOVZ / ADD-SUB-shifted-reg /
fixed). Proven by EXECUTION (the spec-assembled program runs on the sovereign
emulators). Refs: RISC-V Unprivileged ISA, ARMv8-A ARM (encoding tables).
dependencies 1 imports · 2 importers
imports: nx_syscalls_x86_64.nx
imported by: nx_isa_spec_test.nxnx_superopt_general_test.nx
structs
| none |
consts
| 15 | const FMT_RV_R: i64 = 0 // funct7|rs2|rs1|funct3|rd|opcode |
| 16 | const FMT_RV_I: i64 = 1 // imm[11:0]|rs1|funct3|rd|opcode |
| 17 | const FMT_RV_ISHIFT: i64 = 2 // funct6|shamt|rs1|funct3|rd|opcode (RV64 6-bit shamt) |
| 18 | const FMT_A64_MOVZ: i64 = 3 // base | imm16<<5 | Rd |
| 19 | const FMT_A64_ADDSUB:i64 = 4 // base | Rm<<16 | sh<<10 | Rn<<5 | Rd |
| 20 | const FMT_FIXED: i64 = 5 // the whole word is the base (ecall/svc) |
| 34 | const I_RV_ADDI: i64 = 0 |
| 35 | const I_RV_SLLI: i64 = 1 |
| 36 | const I_RV_ADD: i64 = 2 |
| 37 | const I_RV_SUB: i64 = 3 |
| 38 | const I_RV_XOR: i64 = 4 |
| 39 | const I_RV_OR: i64 = 5 |
| 40 | const I_RV_ECALL: i64 = 6 |
| 41 | const I_A64_MOVZ: i64 = 7 |
| 42 | const I_A64_ADD: i64 = 8 |
| 43 | const I_A64_SUB: i64 = 9 |
| 44 | const I_A64_SVC: i64 = 10 |
functions
| 24 | func isa_assemble(fmt: i64, base: i64, f3: i64, f7: i64, rd: i64, a: i64, b: i64, imm: i64) -> i64 called by 1: isa_emit |
| 48 | func isa_emit(inst: i64, rd: i64, a: i64, b: i64, imm: i64) -> i64 |