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nx_loadceil_gate.nx

buildroot/runtime/nx_loadceil_gate.nx

9685 B163 linesdepth 3pulls 4 transitivereach 0 importersview sourcekind gate/proof
docsdependenciesstructsconstsfunctions

about

nx_loadceil_gate.nx -- GATE for the load-ceiling calibrator (LV3). Composes nx_loadceil_lib in-process on PLANTED resmon-log buffers, so every value is asserted with no /proc, no fork and no real log. THE LOAD-BEARING TOOTH is the coupling: recommend * LC_HARD_FACTOR == storm_trigger, and storm_trigger is the GREEN load at the declared quantile. If either drifts from ba_verdict's arithmetic the arming value would land the storm trigger in the wrong place -- so the gate asserts the whole chain, not just that a number came out. NEG-CONTROLS: an all-RED log yields zero green samples -> INSUFFICIENT (never a recommendation from no healthy history); a below-minimum sample -> INSUFFICIENT; RED beats with high load must NOT enter the green distribution (the exact failure that would let a wedge's load calibrate the ceiling that exists to catch wedges).

dependencies 3 imports · 0 importers

nx_syscalls.nx nx_gate_verdict.nx nx_loadceil_lib.nx nx_loadceil_gate.nx

imports: nx_syscalls.nxnx_gate_verdict.nxnx_loadceil_lib.nx

imported by: nobody (leaf or entry point)

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

main gv_ctr sys_mmap nxa_die sys_write sys_exit nxa_lock_take nxa_lock_addr sys_write ↻ nxa_lock_give nxa_lock_addr ↻ nxa_report_overrun sys_write ↻ nxa_dump_printable sys_write ↻ nxa_dump_sizes sys_write ↻ gv_head gv_puts sys_write ↻ sys_mmap ↻ vlg_synth vlg_line vlg_cat vlg_catn sys_mmap ↻ sys_munmap gv_puts ↻ gv_num sys_mmap ↻ sys_write ↻ sys_munmap ↻ gv_subjects gv_puts ↻ gv_num ↻ gv_need gv_puts ↻ lc_recommend lc_recommend_kv sys_mmap ↻

structs

none

consts

21const VLG_SHUFFLE_STRIDE: i64 = 7919
23const VLG_SORTN: i64 = 100

functions

27func vlg_synth(buf: *u8, base: i64, greens: i64, reds: i64, redload: i64) -> i64
called by 1: main calls 1: vlg_line
46func vlg_line(buf: *u8, o0: i64, load: i64, state: *u8) -> i64
called by 1: vlg_synth calls 2: vlg_catvlg_catn
56func vlg_cat(buf: *u8, o0: i64, s: *u8) -> i64 { var o: i64 = o0; var i: i64 = 0; while s[i] != (0 as u8) { buf[o] = s[i]; o = o + 1; i = i + 1 } return o }
called by 1: vlg_line
57func vlg_catn(buf: *u8, o0: i64, v0: i64) -> i64
called by 1: vlg_line calls 2: sys_mmapsys_munmap
69func main() -> i64