nx_mmu_hw.nx

nx_mmu_hw.nx -- GATE: a FAITHFUL x86-64 4-LEVEL PAGE-TABLE WALK MODEL (deepens MEMORY-MGMT toward the real-hw-MMU gap). Where nx_paging is a flat vpn->pfn model, THIS models the ACTUAL x86-64 hardware structures the CPU's MMU walks: a 48-bit VA split 9/9/9/9/12 -> PML4 -> PDPT -> PD -> PT -> frame, CR3-rooted, with present/writable/user/ NX protection bits accumulated down the levels, page faults, and a TLB with invalidation + CR3-flush. This is the rung BEFORE loading a real CR3 -- the exact table layout the hardware expects. ★ NEVER-BRICK (cardinal 26) BY CONSTRUCTION: 100% in-memory integer model over an mmap'd 'simulated physical RAM'. It issues NO real CR3 write, NO privileged instruction, NO MMU/firmware write. The real-hardware activation path (mmu_activate_real) is a STUB that REFUSES by construction -- a real CR3 load requires a SEPARATELY-proven never-brick hardware capability that does not exist here. Proven mechanically in T5, not asserted. T1 4-level walk: map + translate a VA -> exact PA (frame<<12 | offset). T2 unmapped VA -> page fault. T3 protection: a read-only page faults on WRITE (ok on READ); an NX page faults on EXECUTE. T4 TLB: miss->fill->hit; invlpg evicts (miss again); CR3 reload flushes all. T5 NEVER-BRICK teeth: mmu_activate_real is REFUSED by construction (no real CR3 write path exists) + determinism. expect_exit: 0 Sovereign: nx_syscalls.