code wiki / _hdl_build / nx_nishi_riscv_emit.nx
nx_nishi_riscv_emit.nx
buildroot/runtime/_hdl_build/nx_nishi_riscv_emit.nx
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nx_nishi_riscv_emit.nx -- THE PRODUCT LOOP: NishiLang -> RISC-V, run on the QEMU-validated emulator. Invokes the
SOVEREIGN NishiLang RISC-V codegen (nx_riscv_lib `lower`) on a real IR program (triangular sum 1..N), keeps its
computation (result in a0), and swaps the codegen's Linux ecall-exit for a bare-metal UART-emit + SiFive-finisher
epilogue (assembled by the sovereign nx_rv64_asm). Writes the flat binary to knowledge/hw/nishi_rv.bin, to be run on
the QEMU-validated golden sim (nx_rv64_run_bin) AND real qemu-system-riscv64 (the liar-killer). N=5 -> sum 15 = 0x0f.
This closes the loop: NishiLang -> sovereign RISC-V codegen -> QEMU-validated emulator, C/QEMU as the liar-killer.
expect_exit: 0 Sovereign: nx_riscv_lib (codegen) + nx_rv64_asm (assembler) + nx_syscalls.
dependencies 3 imports · 0 importers
imports: nx_riscv_lib.nxnx_rv64_asm.nxnx_syscalls.nx
imported by: nobody (leaf or entry point)
call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown
structs
| none |
consts
| 11 | const K_MAGIC_4096: i64 = 4096 |
functions
| 13 | func g_puts(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 } |
| 14 | func g_pn(v: i64) -> i64 { let b: *u8=sys_mmap(28); var x: i64=v; if x==0{b[0]=48;sys_write(1,b,1);return 0} var d: i64=0; var y: i64=x; while y>0{d=d+1;y=y/10} var i: i64=d-1; y=x; while i>=0{b[i]=(48+(y%10)) as u8;y=y/10;i=i-1} sys_write(1,b,d); return 0 } |
| 15 | func ck(name: *u8, c: i64) -> i64 { if c==1 { g_puts(" PASS " as *u8) } else { g_puts(" FAIL " as *u8) } g_puts(name); g_puts("\n" as *u8); return c } |
| 18 | func build_loop_ir(irop: *i64, irdst: *i64, irs1: *i64, irs2: *i64, irimm: *i64, N: i64) -> i64 called by 1: main |
| 30 | func main() -> i64 |