nx_nishi_usb_kernel.nx

nx_nishi_usb_kernel.nx -- x86 ladder R-KERN-1: the long-mode kernel sets up real GDT + IDT and takes a VECTORED interrupt through the IDT. This is the first OS-internals rung at the long-mode entry the operator chose: lgdt -> a real GDT, lidt -> a real IDT, int -> the CPU vectors through the IDT gate to a handler that runs ONLY because the interrupt was delivered (not a direct call). The kernel is LOADED OFF the persisted image (nishi_os_kernel.img) and booted to LONG mode, then: * builds a spec-shaped GDT (null + 64-bit code [L-bit] + data) as static data, lgdt [pseudo] * builds a spec-shaped IDT whose entry 3 is a real interrupt gate (offset split across the offset_low/offset_mid/offset_high fields, selector 0x08, type 0x8E), lidt [pseudo] * mov rsp + int 3 -> the emu reads IDT[3], reconstructs the handler offset, pushes the return address, and vectors to the handler; the handler writes a marker and IRETs back; HLT. The unified emu now fuses FOUR proven mechanisms: the 16-bit + INT 13h loader, the CR0/EFER mode transition, the 64-bit store/arith engine, and IDT interrupt delivery + iret (from nx_nishios_irq). KAT: (T1) booted off disk; (T2) LONG mode; (T3) GDTR loaded (base+limit); (T4) the GDT holds a 64-bit code descriptor (L-bit set); (T5) IDTR loaded; (T6) int 3 vectored through the IDT -> the handler ran (marker written). NEG/liar-kill (T7): a sibling image whose IDT[3] offset is ZEROED never vectors, so the handler never runs and the marker stays unwritten -- the handler runs ONLY via a real IDT gate. HONEST SCOPE: long mode is flat so the emu loads/validates the GDT but does not enforce segmentation; the IDT delivery (gate read -> reconstruct offset -> push -> vector -> iret) is real. Paging (CR3 + PML4 walk) and PIC/IRQ0 timer preemption are the next two rungs. NEVER-BRICK (Rule 26): writes a FILE; models INT 13h *reads* only; no /dev. expect_exit: 0 license_tier: ORIGINAL