nx_nishi_usb_paging.nx

nx_nishi_usb_paging.nx -- x86 ladder R-KERN-2: the long-mode kernel sets up PAGING (CR3 + 4-level walk). Second OS-internals rung at the long-mode entry. The kernel LOADED OFF the persisted image, after it reaches long mode, BUILDS a 4-level page-table tree IN MEMORY with its own x86 stores (PML4 -> PDPT -> PD -> PT), loads CR3 with `mov cr3, rax`, and HLTs. The emu then performs the long-mode 4-level page walk (VA[47:39]->PML4, [38:30]->PDPT, [29:21]->PD, [20:12]->PT, +[11:0] offset; bit0=present) over the tables the kernel built, and reports the translations -- proving the kernel's page tables are real and walkable. pg_walk is reused verbatim from the proven nx_emu_x86_paging_test (the x86 twin of our rv64 SV39 MMU); the unified emu is extended with `mov cr3` (0F 22 /3). KAT: (T1) booted off disk; (T2) LONG mode; (T3) CR3 loaded with the kernel's PML4 base; (T4) VA 0x1000 translates to PA 0x40000 through the kernel-built tables; (T5) offset preserved (0x1123->0x40123); (T6) a second mapping (0x2000->0x50000); (T7) an unmapped VA faults. NEG/liar-kill (T8): a sibling image whose CR3 is loaded with a WRONG base translates nothing -- so the translations depend on the kernel having built the tables AND loaded the right CR3, not on a constant. HONEST SCOPE: 4KB pages + present bit; long mode is modeled flat so the emu walks the kernel's tables on demand but does not yet route every instruction fetch through the TLB (large pages / A-D bits / permission faults / full MMU routing = refinements). NEVER-BRICK (Rule 26): writes a FILE; INT 13h *reads* only; no /dev. expect_exit: 0 license_tier: ORIGINAL