nx_nishios_kernel_emit.nx

nx_nishios_kernel_emit.nx -- THE COMPOSED NishiOS KERNEL IMAGE (closes the boot adoption gap). THE DEFECT THIS CLOSES: the kernel lane had 26 gate-proven stage binaries (strap / paging / trap_syscall / timer_irq / coopsched / virtio ...), each a SEPARATE tiny image run in isolation -- while the image the pinned BOOTSOV runner actually boots (_boot_nishi_virt.bin) was a 72-byte, 17-step BANNER that exercised NONE of them. Capability proven in a gate but not wired at the live chokepoint IS the baseline. This emitter authors ONE image where the stages FALL THROUGH into a single real boot, so what boots is what was proven. BOOT SEQUENCE (each phase leaves a serial marker; only the last halts): 1 RESET (M) UART up, mtvec + stvec + medeleg installed -> "NISHI " 2 TRAP (M) ecall from M -> kernel trap dispatcher -> mret -> "TRAP " 3 SCHED (M) two tasks, ecall(SYS_YIELD), round-robin mepc swap -> "ABABABABABAB SCHED " 4 TIMER (M) CLINT mtimecmp armed, MIE+MTIE, MTIP preempts the spin -> "TICK " 5 PAGING (S) mret to S-mode, Sv39 root PTEs laid, satp on, VA load -> "PAGE " 6 USER (U) sret to U-mode on a U-bit gigapage, ecall delegated by medeleg to the S-mode handler, sret back, exit syscall -> "USER OK" A real dispatcher: it decodes mcause (interrupt vs exception, ecall-from-M/S/U) and a7 as the syscall number -- not a per-phase hand-installed stub. Failure of any phase prints its own distinct marker (TX / PGX / UX) instead of falling silent, so the gate can never pass vacuously. nx_nishios_kernel_emit [outpath] -> the flat rv64 image + .gold expected transcript Sovereign: syscalls only, no gcc/.sh. license_tier: ORIGINAL