nx_nofloat_hwladder.nx

nx_nofloat_hwladder.nx -- CAP-NF-HWLADDER: the HARDWARE-RUNG-UP ladder, silicon -> AI, each rung grounded on a real organ, with the HARDWARE-CONDITIONAL exceed stated honestly (asterisk-disciplined). The reframe that makes the exceed genuine rather than a niche: on INTEGER-ONLY / NO-FPU hardware (MCUs, FPGAs, RISC-V base ISA, edge) float is a LIABILITY -- it needs an FPU or slow soft-float (hw_fpu: runs "without floating[-point]"; hw_cortexm: Cortex-M0 has no FPU; hw_riscv: integer base ISA, F/D optional; hw_cmsisnn/hw_tflite: the field runs INTEGER on this silicon). Our stack's compiler has NO float type at all -> the AI binary needs ZERO FPU -> NATIVE there. Rungs: R0 SILICON (integer ALU, no-FPU, NEVER-BRICK by construction) -> R1 TOOLCHAIN -> R2 INTEGER MATH -> R3 AUTOGRAD -> R4 TRANSFORMER -> R5 INTEGER-ONLY TRAINING -> R6 EFFICIENT INFERENCE -> R7 SCALE (frontier). T1 R0-R6 each grounded on a real organ (ladder built silicon->AI, contiguous). T2 R7 honestly MISSING (no scale organ -> we do NOT claim the GPU-scale frontier). T3 ASTERISK present: HARDWARE-CONDITIONAL -- EXCEED on no-FPU/edge (float=soft-float), BEHIND on GPU (float wins); the MINORITY path on GPU is the NATIVE path on edge silicon. (carries "MINORITY" for adversary DETECTOR 4) expect_exit: 0 Sovereign: nx_syscalls.