code wiki / (root) / nx_q4k_fused_fidelity_gate.nx

nx_q4k_fused_fidelity_gate.nx

buildroot/runtime/nx_q4k_fused_fidelity_gate.nx

9198 B174 linesdepth 9pulls 23 transitivereach 0 importersview sourcekind gate/prooftopic q4k
docsdependenciesstructsconstsfunctions

about

nx_q4k_fused_fidelity_gate.nx -- DOES THE FUSED INTEGER GEMM TELL THE TRUTH ON REAL TRAINED WEIGHTS? THE QUESTION THIS ANSWERS, AND WHY SPEED CANNOT ANSWER IT. nx_q4k_fused_vs_x4_gate proves the fused kernel is >=9.9x faster and BIT-EXACT -- but only in a synthetic regime built from d=1.0, dmin=0, scales=1 and small integer activations, where every value is exactly representable. That regime is chosen to isolate the KERNEL's logic. It says nothing about REAL weights, because the fused route is not a reassociation: it is ACTIVATION QUANTISATION (f32 -> Q10). Dispatching on the strength of a speed gate would ship fast wrong answers -- the speed bench in this very lane stayed GREEN on a deliberately corrupted kernel. SO THIS GATE IS ADVERSARIAL BY CONSTRUCTION: * REAL weights -- the actual blk.0.attn_q.weight Q4_K super-blocks from the live Qwen3-4B model, with their real trained super-scales and 6-bit sub-scales/mins (nothing synthetic). * Activations DELIBERATELY NOT Q10-REPRESENTABLE. Values are built and then multiplied by the f32 constant 1/3 (0x3EAAAAAB), which has an infinite binary expansion, so every activation carries bits BELOW Q10's 1/1024 resolution. Feeding Q10-exact activations would have flattered the fused path and measured nothing -- the quantisation error would have been zero by construction. * The reference is nx_f32_q4k_matmul_x4: the kernel actually dispatched today, not a strawman. VERDICT UNIT: error is reported in PER-1024 of the reference magnitude (1024 = 100%, 10 ~= 1%), so the actual number is visible and reviewable rather than hidden behind a pass/fail. genealogy_id: nx_q4k_speed_bench (real-model load) + nx_q4k_ggml_kat (2% tolerance discipline)

dependencies 9 imports · 0 importers

nx_syscalls.nx nx_tier.nx nx_le.nx nx_gguf.nx nx_gguf_load.nx nx_f32.nx nx_f32_cvt.nx nx_f32_q4k_matmul.nx nx_gate_verdict.nx nx_q4k_fused_fidelity_gate.nx

imports: nx_syscalls.nxnx_tier.nxnx_le.nxnx_gguf.nxnx_gguf_load.nxnx_f32.nxnx_f32_cvt.nxnx_f32_q4k_matmul.nxnx_gate_verdict.nx

imported by: nobody (leaf or entry point)

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

main gv_ctr sys_mmap gv_head gv_puts sys_write sys_openat_rd ff_puts sys_write ↻ sys_exit sys_mmap ↻ sys_read sys_close nx_gguf_parse nx_le_read_u32 nx_le_read_u64 nx_le_read_u32 ↻ _gguf_skip_value nx_le_read_u64 ↻ nx_le_read_u32 ↻ _gguf_skip_value ↻ sys_mmap ↻ nx_gguf_find_tensor nx_gguf_tensor_at nx_gguf_name_equals nx_gguf_tensor_at ↻ ff_num sys_mmap ↻ sys_write ↻ ff_puts ↻ ff_lcg nx_f32_mul nx_f32_classify nx_f32_exp_field nx_f32_mant_field nx_f32_sign nx_f32_mant_field ↻ nx_f32_exp_field ↻ nx_q10_to_f32 nx_i32_to_f32

structs

none

consts

34const FF_COLS: i64 = 64 // output columns (weight rows) to check
35const FF_ONE_THIRD: i64 = 1051372203 // 0x3EAAAAAB = f32(1/3): forces sub-Q10 bits into every activation

functions

37func ff_puts(s: *u8) -> i64 { var n: i64 = 0; while s[n] != (0 as u8) { n = n + 1 } sys_write(1, s, n); return 0 }
called by 2: ff_nummain calls 1: sys_write
38func ff_num(v: i64) -> i64
called by 1: main calls 3: sys_mmapsys_writeff_puts
48func ff_lcg(s: i64) -> i64 { var v: i64 = s * 1103515245 + 12345; v = v & 2147483647; return v }
called by 1: main
57func ff_max_rel_p1024(ref: *i64, cand: *i64, n: i64) -> i64
82func main(argc: i64, argv: *i64) -> i64