nx_q4k_matmul_mt_gate.nx

nx_q4k_matmul_mt_gate.nx -- adversarial gate for the multi-threaded Q4_K matmul (nx_f32_q4k_matmul_mt / _pool) against the serial oracle nx_f32_q4k_matmul. This is the LLM forward's hot path: the organ recorded "pool (fork-once) is the fix" when fork-per-matmul proved net-slower -- the thread pool IS that fix, landed 2026-07-07. Bit-exactness is a hard requirement and holds by construction (column banding: every C[i,j] computed wholly inside one band, identical accumulation order) -- the gate verifies it with full- buffer i64 compares on POISONED outputs so unwritten columns can never pass. Weight bytes are DUMMY (LCG): nx_q4k_to_f32 decodes any bytes deterministically, so exactness + timing are layout-real without a model file (nx_q4k_matmul_rate precedent). Checks (10): 1 serial oracle OK (m=3, k=512, n=37 -- prime n for band edges) 2..6 MT bit-exact for nworkers in {1,2,3,0=auto,1000=clamp-to-37} 7 m=1 single-token decode shape bit-exact (auto workers) 8..9 caller-owned pool reused across two calls (delta-wait), exact 10 speedup, decode shape m=1 k=1024 n=4864 x6 reps: serial vs POOL path (spawn-once, submit-per-call = the forward's pattern); exact AND wall-time speedup >= floor genealogy_id: substrate_f32_q4k_matmul_v2_parallel + nx_conv2d_mt_gate lineage_id: q4k_matmul_mt_gate_v1