nx_q4k_matmul_x4_gate.nx

nx_q4k_matmul_x4_gate.nx -- adversarial gate for the PACKED-SIMD Q4_K matmul paths (nx_f32_q4k_matmul_x4 / _pool_x4) against the scalar serial oracle nx_f32_q4k_matmul. NUMERIC REGIME: the x4 path sums each output cell as left-to-right 4-lane dot chunks -- a different f32 rounding order than scalar. This gate therefore constructs data where EVERY intermediate sum is an integer with |sum| < 2^24, so f32 addition is EXACT regardless of order and bit-exact comparison across ALL paths is legitimate: * weights: dense synthetic Q4_K blocks with d=1.0 (f16 0x3C00), dmin=0, all 6-bit scales=1, mins=0, LCG nibble bytes -> every dequantized value is an exact integer 0..15; * A: exact small-int f32 (nx_i32_to_f32 of LCG ints). k=512 lanes, |A|<=512, w<=15 -> |cell| <= 512*15*512 = 3.9M < 2^24. Big shape k=1024, |A|<=512 -> <= 7.9M < 2^24. Exact. (ULP-divergent real-model fidelity is witnessed separately by the argmax probe -- " Paris" -- after the dispatcher flip.) pool-x4 vs serial-x4 equality holds on ANY data (identical per-cell order; column banding never splits a cell) -- asserted here too. Checks (10): 1 scalar serial oracle OK (m=3, k=512, n=37 -- prime n) 2 serial-x4 == scalar bit-exact 3 pool-x4 (auto pool) == serial-x4 bit-exact 4 pool-x4 (3-worker pool, odd banding) == serial-x4 5 pool reuse: second call, new A, same pool == fresh serial-x4 6 m=1 decode shape: serial-x4 == scalar 7 wide-A (+-512 ints): serial-x4 == scalar (exact-regime bound) 8 n=1 single-column edge via pool (band clamp) == scalar 9 SPEEDUP ladder on decode shape m=1 k=1024 n=4864: serial-scalar vs pool-scalar vs pool-x4 (all bit-exact vs each other in this regime); floor: pool-x4 >= 2.5x serial-scalar (measured printed) 10 all three big-shape outputs bit-identical genealogy_id: nx_f32x4_mt_matmul (5.0x packed lever) + q4k_matmul_mt_gate lineage_id: q4k_matmul_x4_gate_v1