nx_q5_0_fused_dot_gate.nx

nx_q5_0_fused_dot_gate.nx -- ISOLATED proof of the model-appropriate SOTA decode lever: a FUSED Q5_0 dequant-dot (read the 22-byte block, dequant in-register, dot) vs the CURRENT path (dequant the whole row to F32 i64-slots, then dot). WHY: nx_gguf_typecensus shows our model is 79% Q5_0, but the loader dequants it to F32 i64-slots (8 B/value) -- the memory-bound decode matmul then reads 8 B/value when Q5_0 is 0.69 B/value native = ~11.6x more memory than needed. SOTA (Marlin) keeps weights quantized and dequants in-register. This gate proves the fused kernel bit-exact + measures the memory-bound win at the real FFN shape. Ratio within one run => host-noise-immune. NO forward changes (no " Paris" risk). Checks: 1 fused q5_0 dot == dequant-to-f32-then-dot, bit-exact (whole matmul) 2 fused reads ~11.6x fewer bytes; measure the speedup (floor 1.5x) lineage_id: q5_0_fused_dot_gate_v1