code wiki / _hdl_build / nx_research_conduct.nx

nx_research_conduct.nx

buildroot/runtime/_hdl_build/nx_research_conduct.nx

3317 B43 linesdepth 5pulls 6 transitivereach 0 importersview sourcekind tooltopic research
docsdependenciesstructsconstsfunctions

about

nx_research_conduct.nx -- the NISHI-NATIVE autonomy wiring: admit the research CYCLE through the CONDUCTOR (not cron, not bash, not me hand-running). Per nx_conductor_pulse, recurring work may only fire if ADMITTED: (1) OWNED by an Accountable role -> "researcher" owns the research cycle (cp_owner_ok) (2) GATE-GREEN -> nx_research_gate passes (the 24-index alignment+queryable gate) (cp_run_gate) (3) NEVER-BRICK -> the cycle touches NO hardware (pure files/indexes) -> touches_hw=0 If admitted, the conductor's pulse fires nx_research_cycle on its cadence via cp_fire_governed -- so the whole self-improving loop runs autonomously THROUGH the conductor's governance, exactly like nothing ships except through the publisher. This organ computes + reports the admission (and exits non-zero if REJECTED, so a broken system is never pulsed). Sovereign, no shell. expect_exit: 0 license_tier: ORIGINAL

dependencies 1 imports · 0 importers

nx_conductor_registry.nx nx_research_conduct.nx

imports: nx_conductor_registry.nx

imported by: nobody (leaf or entry point)

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

main rcd_puts cr_is_governed ss_open ss_open2 sys_mmap ss_manifest_dyn ss_manifest_file_dyn sys_mmap ↻ ss_cat ss_readall sys_munmap ss_cat ↻ ss_loadfile sys_map_file sys_openat_rd sys_lseek sys_close ss_readall ↻ ss_load_aux2 sys_mmap ↻ ss_cat ↻ ss_loadfile ↻ ss_r32 sys_munmap ↻ ssl_total_keys ss_r32 ↻ ssl_pow2 ssl_build ss_r32 ↻ ssl_hash_entry ss_r32 ↻ ssl_key_eq ss_r32 ↻ ss_r32 ↻ ssl_lookup ssl_hash_entry ↻ ssl_key_eq ↻ ss_manifest_free sys_munmap ↻

structs

none

consts

none

functions

12func rcd_puts(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 }
called by 1: main
13func rcd_num(v: i64) -> i64 { let bb: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m;sys_write(1,"-" as *u8,1)} let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48;k=1} while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1} var i: i64=0; while i<k{bb[i]=t[k-1-i];i=i+1} sys_write(1,bb,k); return 0 }
called by 1: main
15func main() -> i64