code wiki / _hdl_build / nx_roofline_test.nx

nx_roofline_test.nx

buildroot/runtime/_hdl_build/nx_roofline_test.nx

3781 B57 linesdepth 3pulls 3 transitivereach 0 importersview sourcekind gate/proof
docsdependenciesstructsconstsfunctions

about

nx_roofline_test.nx -- the team DIAGNOSES the real bottleneck of the targets (llama.cpp / ggml), and proves the intelligent lever. Three checks, exit 0 only if all hold: (1) the Q4 quantized MATVEC of single-token decode is MEMORY-bound on a real consumer CPU -- matching the measured reality (AVX2 micro-opt = +0.8%). So SIMD is the WRONG lever. (2) the SAME math, but a batched/reused matmul (each weight reused many times), is COMPUTE- bound -- so the search-governor/superopt IS the right lever there. The roofline tells the team WHICH regime it is in, per kernel, per chip. (3) the data-movement lever (Q4 -> Q2, half the weight bytes) gives ~1.8x in the memory-bound regime -- ~225x more than the SIMD micro-opt. "mental math" (move less) >> brute force. license_tier: ORIGINAL

dependencies 2 imports · 0 importers

nx_roofline.nx nx_syscalls.nx nx_roofline_test.nx

imports: nx_roofline.nxnx_syscalls.nx

imported by: nobody (leaf or entry point)

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

main rt_puts sys_write rt_num sys_mmap sys_write ↻ rf_ridge_milli rf_bound rf_ai_milli rf_byte_speedup_milli sys_mmap ↻ sys_exit

structs

none

consts

none

functions

15func rt_puts(s: *u8) -> i64 { var n: i64 = 0; while s[n] != (0 as u8) { n = n + 1 } sys_write(1, s, n); return 0 }
called by 1: main calls 1: sys_write
16func rt_num(v: i64) -> i64 { let bb: *u8 = sys_mmap(28); var m: i64=v; if m<0 {m=0-m}; let t: *u8 = sys_mmap(28); var k: i64=0; if m==0 {t[0]=48;k=1}; while m>0 {t[k]=48+(m%10); m=m/10; k=k+1}; var i: i64=0; while i<k {bb[i]=t[k-1-i]; i=i+1}; sys_write(1, bb, k); return 0 }
called by 1: main calls 2: sys_mmapsys_write
18func main() -> i64