code wiki / _hdl_build / nx_rv64_jit_ra_gate.nx
nx_rv64_jit_ra_gate.nx
buildroot/runtime/_hdl_build/nx_rv64_jit_ra_gate.nx
about
nx_rv64_jit_ra_gate.nx -- GATE: the REGISTER-ALLOCATED JIT (the SOTA quality step) is CORRECT (equivalent to the
interpreter AND the memory JIT) and keeps block-hot RV64 registers in x86 registers (measured vs the memory-per-op
JIT). Also proves the FAIL-SAFE TIERING: a block that exceeds the register pool is ineligible (-2) -> the caller
falls back to the proven memory JIT (never a miscompile). Closes the register-allocation gap flagged in rung 12.
expect_exit:0
dependencies 4 imports · 0 importers
imports: nx_syscalls.nxnx_rv64_asm.nxnx_rv64_fast.nxnx_rv64_jit.nx
imported by: nobody (leaf or entry point)
call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown
structs
| none |
consts
| none |
functions
| 11 | func g_puts(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 } |
| 12 | func g_pn(v: i64) -> i64 { let b: *u8=sys_mmap(28); var x: i64=v; if x<0{b[0]=45;sys_write(1,b,1);x=0-x} if x==0{b[0]=48;sys_write(1,b,1);return 0} var d: i64=0; var y: i64=x; while y>0{d=d+1;y=y/10} var i: i64=d-1; y=x; while i>=0{b[i]=(48+(y%10)) as u8;y=y/10;i=i-1} sys_write(1,b,d); return 0 } |
| 13 | func ck(name: *u8, c: i64) -> i64 { if c==1 { g_puts(" PASS " as *u8) } else { g_puts(" FAIL " as *u8) } g_puts(name); g_puts("\n" as *u8); return c } |
| 16 | func predec(src: *u8, code: *u8, opk: *i64, rd: *i64, rs1: *i64, rs2: *i64, imm: *i64) -> i64 |
| 22 | func run_ra(opk: *i64, rd: *i64, rs1: *i64, rs2: *i64, imm: *i64, nc: i64, us_out: *i64, reg: *i64) -> i64 |
| 30 | func run_mem(opk: *i64, rd: *i64, rs1: *i64, rs2: *i64, imm: *i64, nc: i64, us_out: *i64, reg: *i64) -> i64 |
| 38 | func run_interp(opk: *i64, rd: *i64, rs1: *i64, rs2: *i64, imm: *i64, nc: i64, us_out: *i64, reg: *i64) -> i64 |
| 45 | func main() -> i64 |