nx_tensor_lower.nx

tensor_lower.nx -- TirGraph -> RV64 asm lowering pass. Bridges the fusion pass (tensor_ir.nx) to actual machine code. Walks the TirGraph in topological order, emitting asm into an OutBuf for each non-fused node. Fused producers are inlined into their consumer's kernel emit -- the headline "comptime fusion" win. v0.0.1 covers: - Element-wise unary/binary ops on i32/i64 tensors (loops) - LOAD: data pointer comes from caller (we just expose it) - PARAM: tensor is a function parameter, address in a-register Out of scope for v0.0.1 (subsequent commits): - MATMUL (triple-nested loop with tile blocking) - ATTENTION (fused softmax+matmul) - fp16/fp32 (waiting on F-extension codegen) - SIMD intrinsics (waiting on RVV codegen) - GPU backends (CUDA / SPIR-V) Each emit follows the standard nxc2 codegen ABI: a0..a7 hold input tensor data pointers the function emits a loop that computes element-by-element