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nx_tensor_placement.nx

buildroot/runtime/nx_tensor_placement.nx

10636 B288 linesdepth 2pulls 2 transitivereach 2 importersview sourcekind librarytopic tensor

docs dependencies structs consts functions

about

nx_tensor_placement.nx -- multi-tier tensor home with promote/demote lifecycle. Per CARDINAL [[feedback-conductor-heterogeneous-compute-no-second-class- resources]]: REFUSES CUDA's VRAM-funnel model. Tensors are first-class multi-tier objects that live where they make sense; the substrate (not the user) routes them between tiers based on cost. V1 ships the placement record (where + how big + last-touched), tier classification + promotion/demotion gates, and aggregate accounting for the dispatcher's cost model.

dependencies 2 imports · 2 importers

imports: nx_syscalls.nxnx_tier.nx

imported by: nx_companion_compose_test.nxnx_tensor_placement_test.nx

structs

43	struct NxTensorPlacement
55	struct NxPlacementRegistry

consts

20	const NX_TP_TIER_VRAM_HOT: nx_int = 0 // GPU memory, active compute
21	const NX_TP_TIER_VRAM_WARM: nx_int = 1 // GPU memory, idle
22	const NX_TP_TIER_RAM_HOT: nx_int = 2 // CPU RAM, active
23	const NX_TP_TIER_RAM_WARM: nx_int = 3 // CPU RAM, idle
24	const NX_TP_TIER_NVME_MMAP: nx_int = 4 // mmap'd file (cold but local)
25	const NX_TP_TIER_SSD_FILE: nx_int = 5
26	const NX_TP_TIER_HDD_FILE: nx_int = 6
27	const NX_TP_TIER_NETWORK_PEER: nx_int = 7 // colder than disk
28	const NX_TP_TIER_N: nx_int = 8
32	const NX_TP_V_OK: nx_int = 0
33	const NX_TP_V_PROMOTED: nx_int = 1
34	const NX_TP_V_DEMOTED: nx_int = 2
35	const NX_TP_V_NO_BUDGET: nx_int = 3 // target tier exceeded budget
36	const NX_TP_V_REFUSED_HOTLOCK: nx_int = 4 // tensor pinned to current tier
37	const NX_TP_V_INVALID: nx_int = 5
38	const NX_TP_V_NULL: nx_int = 6
39	const NX_TP_V_N: nx_int = 7
53	const NX_TP_P_BYTES: nx_int = 56
67	const NX_TP_BYTES: nx_int = 64

functions

71	func nx_tp_tier_is_valid(t: nx_int) -> nx_int called by 4: nx_tp_register nx_tp_promote nx_tp_demote main
77	func nx_tp_v_is_valid(v: nx_int) -> nx_int called by 1: main
83	func nx_tp_tier_is_gpu(t: nx_int) -> nx_int called by 1: main
89	func nx_tp_tier_is_cpu_memory(t: nx_int) -> nx_int called by 1: main
95	func nx_tp_tier_is_cold(t: nx_int) -> nx_int called by 1: main
105	func nx_tp_new(capacity: nx_int, called by 2: main main calls 1: sys_mmap
125	func _tp_at(r: NxPlacementRegistry, idx: nx_int) -> NxTensorPlacement called by 3: nx_tp_find nx_tp_bytes_in_tier nx_tp_count_in_tier
132	func nx_tp_register(r: *NxPlacementRegistry, called by 2: main main calls 1: nx_tp_tier_is_valid
155	func nx_tp_find(r: NxPlacementRegistry, tensor_id: nx_int) -> NxTensorPlacement called by 6: nx_tp_pin nx_tp_unpin nx_tp_touch nx_tp_promote nx_tp_demote main calls 1: _tp_at
168	func nx_tp_pin(r: *NxPlacementRegistry, tensor_id: nx_int) -> nx_int called by 1: main calls 1: nx_tp_find
176	func nx_tp_unpin(r: *NxPlacementRegistry, tensor_id: nx_int) -> nx_int called by 1: main calls 1: nx_tp_find
186	func nx_tp_bytes_in_tier(r: *NxPlacementRegistry, tier: nx_int) -> nx_size called by 3: nx_tp_promote nx_tp_tier_pressure_q10 main calls 1: _tp_at
198	func nx_tp_count_in_tier(r: *NxPlacementRegistry, tier: nx_int) -> nx_int called by 2: main main calls 1: _tp_at
210	func _tp_budget_for_tier(r: *NxPlacementRegistry, tier: nx_int) -> nx_size called by 2: nx_tp_promote nx_tp_tier_pressure_q10
222	func nx_tp_touch(r: *NxPlacementRegistry, tensor_id: nx_int, now_us: nx_size) -> nx_int called by 1: main calls 1: nx_tp_find
237	func nx_tp_promote(r: *NxPlacementRegistry, called by 2: main main calls 4: nx_tp_tier_is_valid nx_tp_find _tp_budget_for_tier nx_tp_bytes_in_tier
256	func nx_tp_demote(r: *NxPlacementRegistry, called by 1: main calls 2: nx_tp_tier_is_valid nx_tp_find
275	func nx_tp_tier_pressure_q10(r: *NxPlacementRegistry, tier: nx_int) -> nx_int called by 1: main calls 2: _tp_budget_for_tier nx_tp_bytes_in_tier