code wiki / _hdl_build / nx_timer_irq_emit.nx
nx_timer_irq_emit.nx
buildroot/runtime/_hdl_build/nx_timer_irq_emit.nx
about
nx_timer_irq_emit.nx -- TIMER-INTERRUPT (preemption mechanism) emitter, the foundation slice
of the preemptive scheduler (kernel-up ladder, toward census GEN-K-preemptive-smp-scheduler).
AUTHOR=ORGAN: table-computes a bare-metal rv64 qemu-virt flat image (zero hand-written machine
code) that installs an mtvec trap vector, prints a BOOT marker, arms the CLINT timer
(MTIMECMP=0x02004000) + enables mie.MTIE/mstatus.MIE, then SPINS. When MTIME reaches MTIMECMP
the CLINT asserts MTIP and the CPU takes the machine-timer trap -> the handler prints a TIMER
marker and clean-halts via the SiFive finisher. PROVES timer-interrupt DELIVERY + handling =
the mechanism preemption is built on. The GOLDEN transcript ("BT") is TABLE-COMPUTED, byte-
reproducibly. Reuses the proven rv64 mini-encoder (same forms as nx_trap_syscall_emit).
nx_timer_irq_emit -> writes runtime/_hdl_build/_timer_irq_virt.bin + .gold
Next slices: re-arm + multi-tick, then 2-task context-switch = the full scheduler.
Sovereign: syscalls only, no gcc/.sh. license_tier: ORIGINAL
dependencies 1 imports · 0 importers
imports: nx_syscalls.nx
imported by: nobody (leaf or entry point)
call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown
structs
| none |
consts
| 15 | const TI_MAGIC_4096: i64 = 4096 |
| 17 | const TI_OUT: *u8 = "runtime/_hdl_build/_timer_irq_virt.bin" |
| 18 | const TI_GOLD: *u8 = "runtime/_hdl_build/_timer_irq_virt.bin.gold" |
| 19 | const TI_LOG: *u8 = "knowledge/status/timer_irq.log" |
| 22 | const TI_UART: i64 = 0x10000000 // NS16550A THR |
| 23 | const TI_FIN: i64 = 0x100000 // SiFive finisher |
| 24 | const TI_PASS: i64 = 0x5555 // FINISHER_PASS -> clean halt |
| 25 | const TI_MTIMECMP: i64 = 0x02004000 // CLINT MTIMECMP[0] |
| 26 | const TI_TICK: i64 = 0x40 // MTIMECMP value (fires after MTIME reaches it) |
| 28 | const TI_MSTATUS: i64 = 0x300 |
| 29 | const TI_MIE: i64 = 0x304 |
| 30 | const TI_MTVEC: i64 = 0x305 |
| 31 | const TI_MIE_MTIE: i64 = 0x80 // mie.MTIE (bit 7) |
| 32 | const TI_MSTATUS_MIE: i64 = 0x08 // mstatus.MIE (bit 3) |
| 34 | const TI_BOOT_CH: i64 = 66 // 'B' |
| 35 | const TI_TIMER_CH: i64 = 84 // 'T' |
| 37 | const RV_X0: i64 = 0 |
| 38 | const RV_T0: i64 = 5 |
| 39 | const RV_T1: i64 = 6 |
| 40 | const RV_T2: i64 = 7 |
| 41 | const RV_T3: i64 = 28 |
functions
| 44 | func ti_lui(rd: i64, imm20: i64) -> i64 { return ((imm20 & 0xFFFFF) << 12) | (rd << 7) | 0x37 } called by 1: main |
| 45 | func ti_auipc(rd: i64, imm20: i64) -> i64 { return ((imm20 & 0xFFFFF) << 12) | (rd << 7) | 0x17 } called by 1: main |
| 46 | func ti_addi(rd: i64, rs1: i64, imm: i64) -> i64 { return ((imm & 0xFFF) << 20) | (rs1 << 15) | (rd << 7) | 0x13 } called by 1: main |
| 47 | func ti_store(rs2: i64, rs1: i64, f3: i64, imm: i64) -> i64 called by 1: main |
| 52 | func ti_jal(rd: i64, imm: i64) -> i64 called by 1: main |
| 59 | func ti_csrrw(rd: i64, csr: i64, rs1: i64) -> i64 { return ((csr & 0xFFF) << 20) | (rs1 << 15) | (1 << 12) | (rd << 7) | 0x73 } called by 1: main |
| 60 | func ti_csrrs(rd: i64, csr: i64, rs1: i64) -> i64 { return ((csr & 0xFFF) << 20) | (rs1 << 15) | (2 << 12) | (rd << 7) | 0x73 } called by 1: main |
| 62 | func ti_w32(buf: *u8, off: i64, w: i64) -> i64 called by 1: main |
| 70 | func ti_p(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 } |
| 71 | func ti_fp(fd: i64, s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(fd,s,n); return 0 } |
| 72 | func ti_fn(fd: i64, v: i64) -> i64 { let bb: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m;sys_write(fd,"-" as *u8,1)}; let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48;k=1}; while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1}; var i: i64=0; while i<k{bb[i]=t[k-1-i];i=i+1}; sys_write(fd,bb,k); return 0 } |
| 74 | func main() -> i64 |