code wiki / _hdl_build / nx_vc_gate.nx

nx_vc_gate.nx

buildroot/runtime/_hdl_build/nx_vc_gate.nx

14236 B298 linesdepth 7pulls 22 transitivereach 0 importersview sourcekind gate/prooftopic vc
docsdependenciesstructsconstsfunctions

about

nx_vc_gate.nx -- ENGINEER gate for nx_video_client_wasm (the browser client core). Runs NATIVELY (same source the WAT target ships) and proves, evidence-driven: - NV1 cross-implementation: containers packed with vc_* validate GREEN under nx_nv1.nx (the team-side authority) and field-for-field match; vc_nv1_next walks exactly the chunks that were packed - wire frames: pack -> parse round-trips kind/id/seq/payload - sample plane: integer IEEE-754 f32->i16 matches known vectors incl. clamp/NaN/Inf/denormal edges; i16->f32 is exact on all 65536 values (round-trips through the inverse map where exactness is defined) - ladder governor: degrade/recover hysteresis decisions license_tier: ORIGINAL

dependencies 2 imports · 0 importers

nx_video_client_wasm.nx nx_nv1_lpc.nx nx_vc_gate.nx

imports: nx_video_client_wasm.nxnx_nv1_lpc.nx

imported by: nobody (leaf or entry point)

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

main g_puts vc_nv1_header vc_wr_u32 vc_nv1_chunk vc_wr_u32 ↻ vc_nv1_end vc_wr_u32 ↻ nv1_validate nv1_rd_u32 g_check g_puts ↻ vc_nv1_validate vc_rd_u32 nv1_write_header nv1_wr_u32 nv1_write_chunk nv1_wr_u32 ↻ nv1_write_end nv1_wr_u32 ↻ vc_nv1_next vc_rd_u32 ↻ vc_wire_pack vc_wr_u32 ↻ vc_wire_parse vc_rd_u32 ↻ vc_f32_bits_to_i16 vc_i16_to_f32_bits vc_i16_to_f32 vc_wr_u32 ↻ vc_i16_to_f32_bits ↻ vc_f32_to_i16 vc_rd_u32 ↻ vc_f32_bits_to_i16 ↻ vc_ladder_step vc_lpc_encode vc_wr_u32 ↻ vc_lpc_rd_i16 vc_lpc_residuals vc_lpc_cost_bits

structs

none

consts

none

functions

17func g_puts(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 }
called by 2: g_checkmain
18func g_check(name: *u8, cond: i64) -> i64
called by 1: main calls 1: g_puts
22func g_pn(v: i64) -> i64
called by 1: main
34func main() -> i64