nx_vcodec_layout_gate.nx

nx_vcodec_layout_gate.nx -- PROVE the vcv-10 MV-plane placement is collision-free in the CLIENT's PACKED context slab at PRODUCTION geometry (F617/seq246). Context: nx_faithdiff proved rct9 lowers to wasm BIT-EXACTLY (VM==native, 0 unfaithful) => the field defect (probe835: rx flowing, dec=-1) is INTEGRATION. The ONE untested seam: every bench/probe gives the MV plane an ISOLATED mmap, but the browser DERIVES it as CX+VV_CTX_MVPLANE (0x32000) INSIDE the shared context slab that also holds the range-coder scratch (CX+0x1800). At 416x320 (the shipped tier) a KEYFRAME's rc section is far larger than any bench frame -- if it overruns 0x32000 it silently clobbers the plane => wrong MV predictors => undecodable P-frames => exactly the observed signature. This gate MEASURES instead of estimating (scale-law: declare the envelope, never assume it): T1 rc high-water: pattern-fill the slab, run key+P with the plane held ISOLATED (so nothing legitimately writes high in the slab), then scan for the HIGHEST byte the codec touched. PASS iff high_water < 0x32000 (the packed placement has real clearance). T2 A/B equivalence: the SAME key+P roundtrip with the plane PACKED (CX+0x32000) vs ISOLATED must produce an IDENTICAL recon checksum. PASS iff equal (packed placement changes nothing). A T1/T2 failure PROVES the collision and mandates the fix shape: give the MV plane its OWN dedicated region passed EXPLICITLY (the proven R_HEAT/heatp pattern), never a base+offset carve. license_tier: ORIGINAL No hw writes (Rule 26). expect_exit: 0