code wiki / _hdl_build / _clksched_probe.nx
_clksched_probe.nx source
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1// _clksched_probe.nx -- throwaway diagnostic (2026-08-03): print EXACTLY what clk_load_plane
2// returns from the production clocksched- plane, plus the min next_due the tickless loop would
3// compute. Ground truth for the slow-beat investigation; run from nishihost cwd. No writes.
4import "nx_clock_sched.nx"
5import "nx_syscalls.nx"
6
7func w(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 }
8func wn(v: i64) -> i64 { var m: i64=v; if m<0{w("-" as *u8);m=0-m} let t:*u8=sys_mmap(24); var k:i64=0; if m==0{t[0]=48 as u8;k=1} while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1} var i:i64=0; let o:*u8=sys_mmap(24); while i<k{o[i]=t[k-1-i];i=i+1} sys_write(1,o,k); return 0 }
9
10func main(argc: i64, argv: *i64) -> i64 {
11 let names: *u8 = sys_mmap(CLK_MAXJOBS*CLK_NAMEW)
12 let orgs: *u8 = sys_mmap(CLK_MAXJOBS*CLK_NAMEW)
13 let iv: *i64 = sys_mmap(CLK_MAXJOBS*8) as *i64
14 let nd: *i64 = sys_mmap(CLK_MAXJOBS*8) as *i64
15 let np: *i64 = sys_mmap(8) as *i64
16 let n: i64 = clk_load_plane("knowledge/store/clocksched-" as *u8, names, orgs, iv, nd, np)
17 w("rows=" as *u8); wn(n); w("\n" as *u8)
18 var i: i64 = 0
19 while i < n {
20 w(clk_slot(names, i)); w(" iv=" as *u8); wn(iv[i]); w(" nd=" as *u8); wn(nd[i])
21 w(" organ=" as *u8); w(clk_slot(orgs, i)); w("\n" as *u8)
22 i = i + 1
23 }
24 var minnd: i64 = nd[0]
25 i = 1
26 while i < n { if nd[i] < minnd { minnd = nd[i] } i = i + 1 }
27 w("min_next_due=" as *u8); wn(minnd); w("\n" as *u8)
28 sys_exit(0)
29 return 0
30}