_gpu_bm_channel_gate.nx source

1// _gpu_bm_channel_gate.nx -- BARE-METAL SOVEREIGN-GPU rung BM-GPU-4: set up a GPFIFO CHANNEL (RAMFC + USERD + 2// GPFIFO ring) and encode a GPFIFO entry that points the FIFO at our pushbuffer. 3// 4// A sovereign driver builds the channel objects the doorbell kicks (nouveau fifo/chan, NVK): RAMFC holds the 5// GPFIFO ring base+size; USERD holds GP_PUT/GP_GET; the GPFIFO ring is an array of 64-bit ENTRIES, each encoding 6// a pushbuffer GPU VA + length (GF100 format: entry0 = va[31:2]<<2 [4-byte aligned]; entry1 = va[39:32] | (len<<10)). 7// NISHI-ECOSYSTEM-ONLY: our model + driver; the GPFIFO entry/channel layout = the last-mile hardware spec. 8// HONEST SCOPE: channel-setup + entry-encode LOGIC vs spec; real channel allocation = BM-GPU-6 on native Linux. 9// 10// GREEN iff: RAMFC GPFIFO_BASE/SIZE configured + read back; the GPFIFO entry ROUND-TRIPS (encode pushbuffer VA+len 11// -> decode == exact VA+len); USERD GP_PUT advanced to 1, GP_GET==0 (one entry pending the kick); AND tampers 12// (corrupted length field / unaligned pushbuffer VA) are correctly DETECTED. 13// Marker -> knowledge/status/gpu_baremetal.log (BMCHANGATE). license_tier: ORIGINAL 14import "nx_syscalls.nx" 15 16func p(s: *u8) -> i64 { var nn: i64=0; while s[nn]!=(0 as u8){nn=nn+1} sys_write(1,s,nn); return 0 } 17func fp(fd: i64, s: *u8) -> i64 { var nn: i64=0; while s[nn]!=(0 as u8){nn=nn+1} sys_write(fd,s,nn); return 0 } 18func n(v: i64) -> i64 { let bb: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m;sys_write(1,"-" as *u8,1)}; let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48;k=1}; while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1}; var i: i64=0; while i<k{bb[i]=t[k-1-i];i=i+1}; sys_write(1,bb,k); return 0 } 19func x(v: i64) -> i64 { p("0x" as *u8); let bb:*u8=sys_mmap(20); var k:i64=0; var m:i64=v; if m==0{bb[0]=48;k=1}; while m>0{ let d:i64=m&15; if d<10{bb[k]=(48+d) as u8}else{bb[k]=(87+d) as u8}; m=(m>>4); k=k+1 } var i:i64=0; let o:*u8=sys_mmap(20); while i<k{o[i]=bb[k-1-i];i=i+1} sys_write(1,o,k); return 0 } 20func fx(fd: i64, v: i64) -> i64 { let bb:*u8=sys_mmap(20); var k:i64=0; var m:i64=v; if m==0{bb[0]=48;k=1}; while m>0{ let d:i64=m&15; if d<10{bb[k]=(48+d) as u8}else{bb[k]=(87+d) as u8}; m=(m>>4); k=k+1 } let o:*u8=sys_mmap(20); var i:i64=0; while i<k{o[i]=bb[k-1-i];i=i+1} fp(fd,"0x" as *u8); sys_write(fd,o,k); return 0 } 21func rd32(b: *u8, o: i64) -> i64 { return (b[o] as i64)|((b[o+1] as i64)<<8)|((b[o+2] as i64)<<16)|((b[o+3] as i64)<<24) } 22func wr32(b: *u8, o: i64, v: i64) -> i64 { b[o]=(v&0xff) as u8; b[o+1]=((v>>8)&0xff) as u8; b[o+2]=((v>>16)&0xff) as u8; b[o+3]=((v>>24)&0xff) as u8; return 0 } 23 24// ===== GF100 GPFIFO entry encode/decode (spec-faithful) ===== 25// entry0 = va[31:0] & ~3 (4-byte aligned pushbuffer addr low); entry1 = va[39:32] | (length_dwords << 10). 26func gp_encode0(va: i64) -> i64 { return va & 0xFFFFFFFC } 27func gp_encode1(va: i64, length: i64) -> i64 { return ((va >> 32) & 0xFF) | ((length & 0x1FFFFF) << 10) } 28func gp_decode_va(e0: i64, e1: i64) -> i64 { return (e0 & 0xFFFFFFFC) | ((e1 & 0xFF) << 32) } 29func gp_decode_len(e1: i64) -> i64 { return (e1 >> 10) & 0x1FFFFF } 30 31func main() -> i64 { 32 p("=== BARE-METAL SOVEREIGN-GPU BM-GPU-4: GPFIFO channel (RAMFC + USERD + ring entry) ===\n" as *u8) 33 // channel state: ch[0]=RAMFC.GPFIFO_BASE ch[1]=RAMFC.GPFIFO_SIZE ch[2]=USERD.GP_PUT ch[3]=USERD.GP_GET 34 let ch: *i64 = sys_mmap(128) 35 let ring: *u8 = sys_mmap(4096) // GPFIFO ring buffer (model), 512 entries * 8B 36 let RING_VA: i64 = 0x400000 // ring buffer GPU VA 37 let RING_ENTRIES: i64 = 512 38 let PB_VA: i64 = 0x32D000 // our pushbuffer (BM-GPU-1) GPU VA 39 let PB_LEN: i64 = 6 // 6 dwords (semaphore-release pushbuffer) 40 41 // ---- sovereign driver: set up the channel ---- 42 ch[0] = RING_VA; ch[1] = RING_ENTRIES; ch[2] = 0; ch[3] = 0 // RAMFC + USERD init 43 // write GPFIFO entry[0] = (encode PB_VA + PB_LEN) 44 wr32(ring, 0, gp_encode0(PB_VA)); wr32(ring, 4, gp_encode1(PB_VA, PB_LEN)) 45 ch[2] = 1 // advance GP_PUT -> 1 entry pending the kick 46 47 // read back + decode (what the FIFO will see) 48 let e0: i64 = rd32(ring, 0); let e1: i64 = rd32(ring, 4) 49 let dec_va: i64 = gp_decode_va(e0, e1); let dec_len: i64 = gp_decode_len(e1) 50 p(" RAMFC: gpfifo_base=" as *u8); x(ch[0]); p(" size=" as *u8); n(ch[1]); p(" | USERD: gp_put=" as *u8); n(ch[2]); p(" gp_get=" as *u8); n(ch[3]); p("\n" as *u8) 51 p(" GPFIFO entry[0]=" as *u8); x(e1); x(e0); p(" -> decode pushbuffer_va=" as *u8); x(dec_va); p(" length=" as *u8); n(dec_len); p(" (expected " as *u8); x(PB_VA); p("/" as *u8); n(PB_LEN); p(")\n" as *u8) 52 53 // ---- TAMPERS ---- 54 // T1: corrupt the length field -> decoded length must differ from PB_LEN (detected) 55 let bad_e1: i64 = gp_encode1(PB_VA, PB_LEN) & 0x3FF // zero the length bits (10..30) 56 var t_len: i64 = 0; if gp_decode_len(bad_e1) != PB_LEN { t_len = 1 } 57 // T2: unaligned pushbuffer VA -> encode loses the low 2 bits -> decode != original (driver must reject) 58 let ua_va: i64 = PB_VA | 0x2 59 let ua_dec: i64 = gp_decode_va(gp_encode0(ua_va), gp_encode1(ua_va, PB_LEN)) 60 var t_align: i64 = 0; if ua_dec != ua_va { t_align = 1 } 61 p(" [tamper] corrupt-length-detected=" as *u8); n(t_len); p(" unaligned-va-detected=" as *u8); n(t_align); p("\n" as *u8) 62 63 var pass: i64 = 0 64 if ch[0] == RING_VA { if ch[1] == RING_ENTRIES { if ch[2] == 1 { if ch[3] == 0 { 65 if dec_va == PB_VA { if dec_len == PB_LEN { if t_len == 1 { if t_align == 1 { pass = 1 } } } } } } } } 66 p(" checks: ramfc_configured=" as *u8); var rc: i64=0; if ch[0]==RING_VA { if ch[1]==RING_ENTRIES { rc=1 } } n(rc) 67 p(" entry_roundtrips=" as *u8); var er: i64=0; if dec_va==PB_VA { if dec_len==PB_LEN { er=1 } } n(er); p(" userd_pending(put1/get0)=" as *u8); var up: i64=0; if ch[2]==1 { if ch[3]==0 { up=1 } } n(up); p(" tampers_ok=" as *u8); var tk: i64=0; if t_len==1 { if t_align==1 { tk=1 } } n(tk); p("\n" as *u8) 68 69 let lfd: i64 = sys_openat_append("knowledge/status/gpu_baremetal.log" as *u8, 0x1a4) 70 if pass == 1 { 71 p("BMCHANGATE verdict=GREEN reason=sovereign-driver-builds-GPFIFO-channel (RAMFC gpfifo_base+size; USERD gp_put=1/gp_get=0; GF100 GPFIFO entry encodes pushbuffer VA 0x32D000 + len 6 and ROUND-TRIPS exactly; corrupt-length + unaligned-VA tampers detected) SCOPE=channel-setup-LOGIC-vs-spec-NOT-real-silicon; real-channel-alloc=BM-GPU-6\n" as *u8) 72 if lfd >= 0 { 73 fp(lfd, "BMCHANGATE verdict=GREEN rung=BM-GPU-4-gpfifo-channel ramfc_gpfifo_base=" as *u8); fx(lfd, ch[0]) 74 fp(lfd, " size=" as *u8); n(ch[1]); fp(lfd, " gp_put=1 gp_get=0 entry_decode_va=" as *u8); fx(lfd, dec_va); fp(lfd, " len=" as *u8); n(dec_len) 75 fp(lfd, " roundtrip=exact tampers=detected(corrupt-length+unaligned-va) scope=channel-setup-logic-vs-spec-NOT-real-silicon next=BM-GPU-5-doorbell->FIFO-fetch-entries->run-pushbuffers\n" as *u8) 76 sys_close(lfd) 77 } 78 sys_exit(0); return 0 79 } 80 p("BMCHANGATE verdict=RED (ramfc/entry-roundtrip/userd/tamper not satisfied)\n" as *u8) 81 if lfd >= 0 { fp(lfd, "BMCHANGATE verdict=RED see-console\n" as *u8); sys_close(lfd) } 82 sys_exit(1) 83 return 1 84}