_gpu_bm_channel_gate.nx

_gpu_bm_channel_gate.nx -- BARE-METAL SOVEREIGN-GPU rung BM-GPU-4: set up a GPFIFO CHANNEL (RAMFC + USERD + GPFIFO ring) and encode a GPFIFO entry that points the FIFO at our pushbuffer. A sovereign driver builds the channel objects the doorbell kicks (nouveau fifo/chan, NVK): RAMFC holds the GPFIFO ring base+size; USERD holds GP_PUT/GP_GET; the GPFIFO ring is an array of 64-bit ENTRIES, each encoding a pushbuffer GPU VA + length (GF100 format: entry0 = va[31:2]<<2 [4-byte aligned]; entry1 = va[39:32] | (len<<10)). NISHI-ECOSYSTEM-ONLY: our model + driver; the GPFIFO entry/channel layout = the last-mile hardware spec. HONEST SCOPE: channel-setup + entry-encode LOGIC vs spec; real channel allocation = BM-GPU-6 on native Linux. GREEN iff: RAMFC GPFIFO_BASE/SIZE configured + read back; the GPFIFO entry ROUND-TRIPS (encode pushbuffer VA+len -> decode == exact VA+len); USERD GP_PUT advanced to 1, GP_GET==0 (one entry pending the kick); AND tampers (corrupted length field / unaligned pushbuffer VA) are correctly DETECTED. Marker -> knowledge/status/gpu_baremetal.log (BMCHANGATE). license_tier: ORIGINAL