topic: gpu

76 modules sharing the gpu name family (derived from the tree's prefix discipline).

The 'gpu' topic family in the Nishi sovereign ecosystem provides foundational support for bare-metal GPU operations within the NishiLang framework, organizing 75 modules into distinct rungs for system bring-up and functional execution. Modules like _gpu_bm_gpfifo_gate establish the GPFIFO interface, while _gpu_bm_pci_gate handles PCIe enumeration and GPU identification, and _gpu_bm_gmmu_gate manages VA-to-PA translation through the GMMU. These modules collectively enable low-level GPU control, memory management, and communication pathways essential for sovereign GPU execution in the Nishi architecture.

auto-narrated by the local model from this topic's module headers; links verified against the wiki index.

narrated overview -- maintained by the narration lane, module links verified against this wiki.

module	description	lines	funcs
_gpu_bm_boot_gate.nx	BARE-METAL SOVEREIGN-GPU rung BM-GPU-3: GPU bring-up over the BAR0 MMIO register file.	91	10
_gpu_bm_channel_gate.nx	BARE-METAL SOVEREIGN-GPU rung BM-GPU-4: set up a GPFIFO CHANNEL (RAMFC + USERD +	84	12
_gpu_bm_compute_gate.nx	BARE-METAL SOVEREIGN-GPU rung BM-GPU-C1: compute-class dispatch + GEMM through the	155	10
_gpu_bm_copy_gate.nx	BARE-METAL SOVEREIGN-GPU rung BM-GPU-CE1: Copy Engine (DMA) through the sovereign GPFIFO.	128	10
_gpu_bm_doorbell_gate.nx	BARE-METAL SOVEREIGN-GPU rung BM-GPU-5: the FULL doorbell->execute path.	128	15
_gpu_bm_gmmu_gate.nx	BARE-METAL SOVEREIGN-GPU rung BM-GPU-MMU: the NVIDIA GMMU (GPU page tables) VA->PA	123	13
_gpu_bm_gpfifo_gate.nx	BARE-METAL SOVEREIGN-GPU rung BM-GPU-1: a spec-accurate sovereign NVIDIA GPFIFO	119	10
_gpu_bm_pci_gate.nx	BARE-METAL SOVEREIGN-GPU rung BM-GPU-2: PCIe config-space enumeration + GPU identify +	121	13
_gpu_bm_qmd_gate.nx	BARE-METAL SOVEREIGN-GPU rung BM-GPU-C2: FAITHFUL Ampere+ compute QMD-by-pointer dispatch	149	11
_gpu_bm_qmd_v5_gate.nx	BARE-METAL SOVEREIGN-GPU rung BM-GPU-7a: REAL Blackwell QMDV05_00 descriptor.	208	13
_gpu_compute_gate.nx	GPU-COMPUTE bit-identical CPU-vs-GPU gate (V-RAM-005 / X-DRV-003, the	188	10
_gpu_deploy_pcienum.nx	BARE-METAL DEPLOYMENT KIT rung BM-DEPLOY-1: REAL PCI enumeration via /proc/bus/pci/devices.	96	8
_gpu_dxg_adapterinfo_gate.nx	SOVEREIGN-GPU ladder R1 (adapter identity), the HONEST re-scope.	125	6
_gpu_dxg_alloc_gate.nx	SOVEREIGN-GPU ladder R4d (allocate REAL GPU memory on the 5080, UMD-less).	141	14
_gpu_dxg_context_gate.nx	SOVEREIGN-GPU ladder R4a (create a GPU CONTEXT on the 5080 WDDM device).	133	11
_gpu_dxg_device_gate.nx	SOVEREIGN-GPU ladder R3 (create a real WDDM DEVICE on the RTX 5080).	141	10
_gpu_dxg_gate.nx	GATE for the SOVEREIGN-GPU foundation rung (R0): proves Nishi reaches the	98	6
_gpu_dxg_gate_tamper.nx	NO-FALSE-GREEN PROOF for _gpu_dxg_gate. Identical logic, EXCEPT the	46	5
_gpu_dxg_makeresident_gate.nx	SOVEREIGN-GPU ladder R4f (make a real allocation GPU-RESIDENT on the 5080).	164	18
_gpu_dxg_mapva_gate.nx	SOVEREIGN-GPU ladder R4e (map a real allocation to a GPU VIRTUAL ADDRESS on the 5080).	165	18
_gpu_dxg_open_gate.nx	SOVEREIGN-GPU ladder R2 (adapter-handle open from LUID).	137	8
_gpu_dxg_pagingqueue_gate.nx	SOVEREIGN-GPU ladder R4c (create a GPU PAGING QUEUE + fence on the 5080).	141	12
_gpu_dxg_r1_recon.nx	SCOPE/RECON probe for SOVEREIGN-GPU rung R1: adapter DESCRIPTION +	205	8
_gpu_dxg_r1_recon2.nx	R1 recon pass 2. nr=0x09 (LX_DXQUERYADAPTERINFO, code 0xC0184709) is	107	7
_gpu_dxg_r1_recon3.nx	R1 recon pass 3. Pass 2 proved QueryAdapterInfo(nr=0x09) returns	131	7
_gpu_dxg_r1_recon4.nx	R1 recon pass 4. GROUND TRUTH from WSL2-Linux-Kernel	118	8
_gpu_dxg_r1_recon5.nx	R1 recon pass 5: confirm the NO-FALSE-GREEN tamper behavior for the	68	5
_gpu_dxg_r2_recon.nx	SOVEREIGN-GPU ladder R2 RECON (adapter-open from LUID).	100	6
_gpu_dxg_r3_recon.nx	SOVEREIGN-GPU ladder R3 RECON (create a WDDM device on the RTX 5080).	103	8
_gpu_dxg_r4_recon.nx	SOVEREIGN-GPU ladder R4 RECON (create a GPU CONTEXT on the WDDM device).	92	10
_gpu_dxg_r4b_recon.nx	SOVEREIGN-GPU ladder R4b RECON (read the REAL VRAM budget of the 5080).	75	8
_gpu_dxg_r4c_pq_recon.nx	SOVEREIGN-GPU ladder R4c RECON (create a GPU PAGING QUEUE on the 5080).	84	10
_gpu_dxg_r4c_recon.nx	SOVEREIGN-GPU ladder R4c RECON (allocate real GPU memory on the 5080).	79	9
_gpu_dxg_r4d_alloc.nx	SOVEREIGN-GPU ladder R4d ATTEMPT: real UMD-less EXISTINGHEAP allocation on the 5080.	106	12
_gpu_dxg_r4d_alloc2.nx	SOVEREIGN-GPU ladder R4d ATTEMPT 2: tune the EXISTINGHEAP standard allocation.	94	12
_gpu_dxg_r4d_alloc3.nx	SOVEREIGN-GPU ladder R4d ATTEMPT 3: provide the per-alloc OUT priv_drv_data buffer.	95	12
_gpu_dxg_r4d_alloc4.nx	SOVEREIGN-GPU R4d CONFIRM: the EXACT EXISTINGHEAP recipe from the open-source	83	11
_gpu_dxg_r4d_probe.nx	SOVEREIGN-GPU ladder R4d PROBE pass 1: locate alloc_count in d3dkmt_createallocation.	87	9
_gpu_dxg_r4d_probe2.nx	SOVEREIGN-GPU ladder R4d PROBE pass 2: locate the allocation_info pointer.	87	9
_gpu_dxg_r4d_probe3.nx	SOVEREIGN-GPU ladder R4d PROBE pass 3: characterize the d3dkmt_allocationinfo2	84	9
_gpu_dxg_r4d_probe4.nx	SOVEREIGN-GPU ladder R4d PROBE pass 4: find the StandardAllocation flag bit	103	11
_gpu_dxg_r4e_map_recon.nx	SOVEREIGN-GPU ladder R4e RECON: map the R4d allocation to a GPU VA on the 5080.	104	14
_gpu_dxg_r4e_recon.nx	SOVEREIGN-GPU ladder R4e RECON: reserve GPU virtual-address space on the 5080.	78	11
_gpu_dxg_r4e_wait_recon.nx	SOVEREIGN-GPU R4e RECON: confirm the paging fence ADVANCES to the map's	101	14
_gpu_dxg_r4f_recon.nx	SOVEREIGN-GPU ladder R4f RECON: make the R4d allocation GPU-RESIDENT on the 5080.	102	14
_gpu_dxg_r4g_recon.nx	SOVEREIGN-GPU ladder R4g RECON: create a GPU SYNCHRONIZATION OBJECT on the 5080.	86	11
_gpu_dxg_r4g_size.nx	R4g size-sweep: find the real _IOC_SIZE for CREATESYNCHRONIZATIONOBJECT (nr=0x10).	77	10
_gpu_dxg_r4g_sw_recon.nx	R4g RECON: signal+wait a monitored-fence sync object from CPU.	98	12
_gpu_dxg_r5_submit_size.nx	R5 SAFE size-sweep for LX_DXSUBMITCOMMAND (nr=0x0f). The submit validation	73	10
_gpu_dxg_r5a_fence.nx	SOVEREIGN-GPU R5a-v2: prove the real 5080 EXECUTES a Nishi-emitted pushbuffer by	141	17
_gpu_dxg_r5a_probe.nx	R5a SUBMIT offset probe (SAFE): find broadcast_context_count + broadcast_context[0]	119	17
_gpu_dxg_r5a_sem.nx	SOVEREIGN-GPU R5a: make the real RTX 5080 EXECUTE a Nishi-emitted pushbuffer.	152	17
_gpu_dxg_r6_hwq.nx	SOVEREIGN-GPU R6: make the real RTX 5080 EXECUTE via the HARDWARE-QUEUE path.	85	4
_gpu_dxg_syncobj_gate.nx	SOVEREIGN-GPU ladder R4g (GPU synchronization-object mechanism on the 5080).	146	16
_gpu_dxg_vidmem_gate.nx	SOVEREIGN-GPU ladder R4b (read the REAL VRAM budget of the 5080).	121	10
_gpu_matmul_gate.nx	GPU 2x2 int8 MATMUL bit-identical CPU-vs-GPU gate (V-RAM-005 / X-DRV-003,	185	10
_gpu_oplist_gate.nx	GPU-class driver-from-spec gate (X-DRV-W1 -> X-DRV-003 / GPU trajectory):	168	11
_gpu_run.nx	a SOVEREIGN rv64 runner with the GPU-class device ATTACHED (twin of	85	3
nx_gpu_bench.nx	SOVEREIGN three-way GPU-compute benchmark harness: OURS vs CUDA vs Vulkan,	270	9
nx_gpu_broker.nx	THE RESOURCE-SHARING BRAIN (serving-census capstone). Admits/schedules a MIXED workload --	154	13
nx_gpu_ctl.nx	SOVEREIGN GPU-provider CONTROL PLANE (Vast.ai) over our OWN TLS-1.2 stack (console.vast.ai is	102	10
nx_gpu_driver.nx	SOVEREIGN UNIVERSAL GPU-DRIVER FRAMEWORK (operator: "not just our own gpu driver but all of	84	10
nx_gpu_dxg_probe.nx	SOVEREIGN-GPU foundation organ (R0): reach the REAL RTX 5080 through	123	7
nx_gpu_embed_gate.nx	E-ARC e4 (2026-07-15): the NISHILANG GPU-EMBED CLIENT, gated BIT-EXACT	231	9
nx_gpu_exceed_gate.nx	MEASURED DirectX exceed: the sovereign graphics SUBMISSION path vs DirectX.	88	6
nx_gpu_export.nx	dump the no-float Qwen2.5-0.5B i8 caches + i32 head + output_norm gamma + freqs +	131	7
nx_gpu_geometry.nx	GOAL-GPU-NATIVE rung-3: the 3D GEOMETRY STAGE (transform + project + hidden-surface).	124	12
nx_gpu_graphics_gate.nx	GOAL-GPU-NATIVE rung-2: a GRAPHICS engine on the sovereign GPFIFO pipeline.	170	16
nx_gpu_matcher.nx	sovereign GPU-provider MATCHER for our exact sovereign-development spec (verified 2026-07-14).	46	4
nx_gpu_power.nx	sovereign GPU POWER + THERMAL GOVERNOR (operator 2026-06-20: "fix the energy and heat output	30	2
nx_gpu_power_gate.nx	gate for the sovereign GPU power/thermal governor (nx_gpu_power) = the NEVER-FRY rung.	40	5
nx_gpu_q4k_gate.nx	proves a SOVEREIGN organ can drive the GPU.	335	10
nx_gpu_render.nx	SOVEREIGN SOTA-render R1: the WebGL2 BEACHHEAD. Emits a self-contained HTML that renders	50	2
nx_gpu_ring.nx	GATE: a GPU BAR/MMIO COMMAND-RING SUBMISSION MODEL (deepens GPU-DRIVER toward the real-hw BAR/ring	147	14
nx_gpu_serve_gate.nx	#23 KEYSTONE: the SOVEREIGN serve-side GPU client, gated byte-exact.	149	8
nx_gpu_sovereignty_gate.nx	ADVERSARIAL proof of the operator's "NO 3rd party" law for the browser-COMPAT	90	5